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Visual computer-aided chip design and simulation verification method and system

A computer-aided, simulation verification technology, applied in computer-aided design, calculation, special data processing applications, etc., can solve the problems of slow calculation speed, incomplete simulation, slow circuit simulation speed, etc., to improve accuracy and improve simulation verification Speed, the effect of ensuring accuracy

Active Publication Date: 2021-10-15
SUZHOU BATELAB MICROELECTRONICS
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, if the simulated circuit is a complex circuit, the calculation speed of such a matrix in related technologies will be very slow due to the large amount of matrix data obtained after the matrix conversion of the complex circuit, and correspondingly, the circuit simulation speed is also very slow
In addition, the simulation in the EDA software is after all calculated by the computer, and the computer cannot completely simulate all the parameters that exist in the actual situation during the calculation process. Therefore, there is a large possibility of error between the calculated simulation results and the actual situation.

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  • Visual computer-aided chip design and simulation verification method and system
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  • Visual computer-aided chip design and simulation verification method and system

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Embodiment Construction

[0054] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0055] The terms "first", "second", "third", and "fourth" in the specification and claims of this application and the above drawings are used to distinguish different objects, rather than to describe specific order. Furthermore, the terms "comprising" and "having", and any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or device comprisin...

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Abstract

The invention discloses a visual computer-aided chip design and simulation verification method and system. The method comprises the following steps: in response to a circuit design instruction of a user on a visual page, generating a virtual circuit structure; and converting the virtual circuit structure into a control signal conforming to a preset format condition, decoding the control signal by using a decoding method matched with the preset format condition, and generating a circuit adjusting signal according to a decoding result. The circuit adjusting signal is sent to an entity circuit generator of the integrated circuit component, and the entity circuit generator adjusts the connection relation between each circuit component and each node integrated on the entity circuit generator based on the circuit adjusting signal so as to generate an entity circuit structure used for simulation verification operation. The circuit simulation verification efficiency can be effectively improved, and the accuracy of a circuit simulation verification result is improved.

Description

technical field [0001] The present application relates to the technical field of electrical digital data processing, in particular to a visual computer-aided chip design and simulation verification method and system. Background technique [0002] EDA (Electronic Design Automation, Electronic Design Automation) technology uses computers as tools. Designers use the hardware description language VHDL to complete design files on the EDA software platform, and then the computer automatically completes logic compilation, simplification, segmentation, synthesis, and optimization. , layout, routing and simulation, as well as adaptation compilation, logic mapping and programming download for specific target chips. This technology can greatly improve the efficiency and operability of circuit design, and reduce the labor intensity of designers. Related technologies are currently designing and simulating circuits in EDA software. [0003] The method of performing circuit simulation in...

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Application Information

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IPC IPC(8): G06F30/367
CPCG06F30/367G06F30/31
Inventor 不公告发明人
Owner SUZHOU BATELAB MICROELECTRONICS