Method for improving threshold voltage adaptation and alternating current performance of FinFET device

Abstract

The invention provides a method for improving threshold voltage adaptation and alternating current performance of a FinFET device. The method comprises the steps of enabling a grid structure to be located between a source region epitaxial region and a drain region epitaxial region; enabling a first interlayer dielectric layer to cover the grid structure; planarizing the grid structure to expose the top of the grid; performing back etching on the metal grid and the work function layer to form a groove; depositing a first barrier layer covering the groove, the grid structure and the first interlayer dielectric layer; forming an oxygen plug in the groove, and depositing a second barrier layer covering the first interlayer dielectric layer, the grid structure and the oxygen plug; forming a second interlayer dielectric layer on the second barrier layer; and leading out contact lines respectively from the source region epitaxial region and the drain region epitaxial region. The alternating current performance of the device can be improved; fluorine is prevented from entering the high-K dielectric layer and reacting with oxygen to deteriorate the threshold voltage of the device; the isolation performance from the grid electrode to the metal layer is improved, and the yield of the SRAM and the logic circuit is increased; the process is simplified; the occurrence of cavities in the embolism is avoided; and the blocking effect is improved.

Description

technical field

[0001] The invention relates to the technical field of semiconductors, in particular to a method for improving threshold voltage adaptation and AC performance of FinFET devices. Background technique

[0002] In the FINFET manufacturing process in the prior art, SiN is usually used as the gate plug. The advantage of using SiN plug is that it can improve the AC performance of the device; it can reduce oxygen, and fluorine enters the HK layer to react with oxygen, deteriorating the threshold voltage of the device. ; Improve gate to metal layer isolation performance, improve the yield of SRAM and logic circuits.

[0003] However, the use of SiN plugs also has the following problems: the deposition of SiN plugs usually has voids, especially when the technology node shrinks below 20nm; when SiN plugs are ground, their residues will enter SiN voids, resulting in increased defects; During the etching process of the gate contact hole, the SiN plug will be broken due ...

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