Driving circuit of low-side NMOS (N-channel metal oxide semiconductor)

Abstract

The invention provides a driving circuit of a low-side NMOS (N-channel Metal Oxide Semiconductor), which is characterized in that a driving discharging module and a driving charging module are combined, the grid current of the low-side NMOS is dynamically adjusted according to a switching control signal of the low-side NMOS and a switching stage of the low-side NMOS, so that the low-side NMOS is charged or discharged at a preset current when being in a non-Miller platform stage. Therefore, the low-side NMOS is driven at low resistance, the switching delay is reduced, and the anti-interference performance of the low-side NMOS is improved.

Description

technical field [0001] The invention belongs to the technical field of power electronics, and more specifically, relates to a low-side NMOS drive circuit. Background technique [0002] like figure 1 As shown, a load and a low-side NMOS are connected in series between the power supply and the reference ground; the control terminal of the low-side NMOS is connected to the driving circuit; the low-side NMOS is used to drive resistive and inductive loads. In practical applications, in order to reduce the electromagnetic interference caused by low-side NMOS, it is necessary to control the slew rate of the switch point, that is, ΔV / Δt, ΔV is the voltage difference, and Δt is the change time. [0003] like figure 2 As shown, it shows the Miller plateau effect of the low-side NMOS turn-on stage, and it can be seen that the voltage change of the drain occurs in a plateau stage when the gate voltage is higher than the threshold voltage Vth, as shown in figure 2 The t3 stage is sh...

AI Technical Summary

Problems solved by technology

first in figure 2 In the t1 and t2 stages, the drive current to the gate is not enough. When the turn-on signal comes, the delay in the t1 and t2 stages will affect the turn-on speed of the low-side NMOS; secondly, when the Miller platform ends, if figure 2 In the stage after t3 shown, the driving current to the gate is not enough, and the low-side NMOS is not fully turned on

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