Clock data recovery circuit

Abstract

The invention provides a clock data recovery circuit. The clock data recovery circuit includes a phase blender, a phase detector, a data sampling position detector and a data selector. The phase blender generates a third clock signal and a fourth clock signal according to a first clock signal and a second clock signal. The phase detector samples a data signal according to the first and second clock signals to generate first sampled data, second sampled data and a phase state signal. The data sampling position detector samples the data signal according to the third and fourth clock signals to generate third sampled data, fourth sampled data and a control signal. The data selector generates output data according to the control signal and the phase state signal.

Description

technical field [0001] The invention relates to a clock data recovery circuit, in particular to a clock data recovery circuit capable of improving signal jitter tolerance. Background technique [0002] In the data signal transmission operation, the clock signal is often adjusted in conjunction with the data signal. However, during the transmission process, the data signal and the corresponding clock signal are often deviated due to signal jitter, resulting in the problem that the data signal cannot be transmitted correctly. [0003] In the known technology, a clock data recovery circuit is often used to overcome the above-mentioned problems. However, the known clock and data recovery circuits often require complex circuits or calculation methods to perform the adjustment action between the data signal and the clock signal, which causes a certain burden in terms of design difficulty and circuit cost. Contents of the invention [0004] The invention is aimed at a clock dat...

AI Technical Summary

Problems solved by technology

The phase mixer generates a third clock signal and a fourth clock signal according to the first clock signal and the second clock signal

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