Semiconductor structure, forming method thereof and method for detecting offset by using semiconductor structure

A semiconductor and conductive structure technology, applied in the field of semiconductor structure and its formation, can solve problems such as large human error, inability to clearly and effectively respond to OVL, rough in-line measurement, etc., to reduce error, reduce contact, and eliminate increased sensitivity Effect

Pending Publication Date: 2021-12-07
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology

Existing OVL testing is mainly divided into inline measurement and Wafer Acceptance Test (WAT). Among them, inline measurement is relatively rough and has large human errors, while traditional wafer acceptance The test can only provide a qualitative test, neither of which can clearly and effectively reflect the specific value of the OVL from the conductive structure to the gate structure

Method used

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  • Semiconductor structure, forming method thereof and method for detecting offset by using semiconductor structure
  • Semiconductor structure, forming method thereof and method for detecting offset by using semiconductor structure
  • Semiconductor structure, forming method thereof and method for detecting offset by using semiconductor structure

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Embodiment Construction

[0045] The following description provides specific application scenarios and requirements of the application, with the purpose of enabling those skilled in the art to manufacture and use the contents of the application. Various local modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and embodiments without departing from the spirit and scope of the disclosure. application. Thus, the present disclosure is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.

[0046] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. For example, as used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. When used in this specification, the terms "comprises", "com...

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Abstract

The invention discloses a semiconductor structure, a forming method thereof and a method for measuring offset by using the semiconductor structure. The semiconductor structure comprises a substrate; a first resistor structure which is located on the surface of the substrate and extends in the first direction; a second resistor structure which is located on the surface of the substrate and extends in the first direction, wherein the shape and the size of the second resistor structure are the same as those of the first resistor structure; a first terminal, a second terminal and a third terminal which are located on the surface of the first resistor structure at intervals in the first direction; a fourth terminal, a fifth terminal and a sixth terminal which are located on the surface of the second resistor structure at intervals in the second direction; and a plurality of interconnection structures which are electrically connected with the first terminal, the second terminal, the third terminal, the fourth terminal, the fifth terminal, and the sixth terminal to form a Wheatstone bridge. According to the semiconductor structure, the forming method thereof and the method for measuring the offset by using the semiconductor structure disclosed by the invention, the quantitative detection of the OVL offset is realized.

Description

technical field [0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method for forming the same, and a method for detecting offset using the semiconductor structure. Background technique [0002] With the development of semiconductor technology, the integration level of VLSI chips has reached the scale of billions or even tens of billions of devices, and the alignment between layers is very important. For products with a critical dimension of 130nm and below, the distance from the conductive structure (CT) to the gate structure (Gate) is very small, and the alignment of the two is very important. [0003] Overlay index (Over-layer, OVL) is used to illustrate the degree of alignment between different layers, and it is also a very critical parameter in the manufacturing process. Existing OVL testing is mainly divided into inline measurement and Wafer Acceptance Test (WAT). Among them, inline measur...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/544H01L21/66H01L21/82
CPCH01L22/34H01L22/14H01L22/12H01L21/82
Inventor 廖黎明仇峰王雪梅
Owner SEMICON MFG INT (SHANGHAI) CORP
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