Semiconductor device and preparation method thereof

A semiconductor and device technology, applied in the field of semiconductor devices and their preparation, can solve problems such as double hump in the drain current-gate voltage curve, and achieve the effects of improving the double hump phenomenon, increasing the voltage threshold, and inhibiting early turn-on

Pending Publication Date: 2021-12-24
YANGTZE MEMORY TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] In the integrated circuit manufacturing process, it is easy to cause the double hump phenomenon of the drain current-gate voltage curve

Method used

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  • Semiconductor device and preparation method thereof
  • Semiconductor device and preparation method thereof
  • Semiconductor device and preparation method thereof

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Embodiment Construction

[0036] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts belong to the protection scope of the present invention.

[0037] It will be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, a first component could be termed a second component, and, similarly, a second component could be termed a first component, without departing from the scope of the present invention.

[0038] It will be understoo...

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Abstract

The present invention discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate and a grid electrode located on the substrate, the substrate comprises an active region arranged in the first direction and isolation regions located at the two sides of the active region in the second direction, and the grid electrode extends to the isolation regions at the two sides of the active region in the second direction. The grid electrode is provided with first-type doped ions and is provided with a second-type doped region corresponding to the junction of the active region and the isolation regions. The doping type of the second-type doped region is opposite to the type of the first-type doped ions in the grid electrode, so that an electric field at the edge of the active region can be reduced, namely, a channel edge region corresponding to the edge of the active region is more difficult to open or the inversion time is later, and accordingly the channel edge region can be prevented from being opened in advance, namely the voltage threshold value of the channel edge region is improved, and the double-hump phenomenon of an Id-Vg curve is improved.

Description

technical field [0001] The present invention generally relates to electronic devices, and more particularly, to a semiconductor device and a method of manufacturing the same. Background technique [0002] In some existing semiconductor devices, it is often necessary to have the following transistors: a low voltage MOS transistor (Low Voltage Metal Oxide Semiconductor, LVMOS) and a high voltage MOS transistor (High Voltage Metal Oxide Semiconductor, HVMOS). A shallow trench isolation structure (Shallow Trench Isolation, STI) is an important component in an integrated circuit, and the STI is formed in a substrate to isolate electrical connections between MOS (Metal Oxide Semiconductor) transistors. [0003] In the integrated circuit manufacturing process, it is easy to cause the double hump phenomenon of the drain current-gate voltage curve. Contents of the invention [0004] The purpose of the present invention is to provide a semiconductor device and a method for preparin...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/49H01L21/28H01L27/088H01L21/8234
CPCH01L29/4983H01L21/28008H01L27/088H01L21/823437
Inventor 石艳伟
Owner YANGTZE MEMORY TECH CO LTD
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