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Memory-limited digital circuit parallel static learning method and system

A technology of digital circuits and learning methods, applied in the field of data processing, to achieve the effect of improving effective utilization, avoiding memory, and improving running speed

Pending Publication Date: 2022-01-11
SHANTOU UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] The purpose of the present invention is to provide a parallel static learning method and system for digital circuits under memory constraints, to solve one or more technical problems in the prior art, and at least provide a beneficial choice or create conditions

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  • Memory-limited digital circuit parallel static learning method and system

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Embodiment Construction

[0051] The concept, specific structure and technical effects of the present application will be clearly and completely described below in conjunction with the embodiments and drawings, so as to fully understand the purpose, scheme and effect of the present application. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0052] When the inventor was conducting research on static learning, he found that the existing single-thread implementation had the problem of too long running time. In response to this problem, the inventor extracted the place that can be implemented in parallel in the static learning process, and proposed a new parallel implementation method for static learning based on the premise of limited memory, which can not only avoid consuming a large amount of memory, but also greatly improve static learning. The speed at which learning runs.

[0053] ...

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Abstract

The invention relates to the technical field of data processing, in particular to a memory-limited digital circuit parallel static learning method and system, and the method comprises the steps: scanning a digital circuit, and collecting all learning tasks needing to be learned in the digital circuit; storing the learning tasks in an array and dividing the learning tasks into a plurality of groups; creating a plurality of parallel threads, and distributing a common event queue for all the parallel threads; acquiring events excited by the learning tasks in the learning task group, and putting the events into an event queue; enabling all the threads to carry out parallel static learning on events in the event queue together; after all the threads finish one learning task group together, determining whether an unfinished learning task group exists or not, and if yes, selecting one learning task group from the unfinished learning task group for learning; otherwise, enabling all the threads to stop working. Static learning is realized in a parallel mode on the premise of occupying less memory space, and the running speed of static learning is greatly improved.

Description

technical field [0001] The invention relates to the technical field of data processing, in particular to a method and system for parallel static learning of digital circuits under memory constraints. Background technique [0002] Digital circuit design needs to pass test simulation before tape-out to ensure the correctness and integrity of the design of the digital circuit sent to the chip. Therefore, test simulation plays a key role in digital circuit design. ATPG (automatic test pattern generation, automatic test pattern generation) is a process in which test vectors used in digital circuit testing are automatically generated by a program, and plays an important role in digital circuit testing. Static learning is an algorithm for identifying additional implicitly derived relationships between logic gates in digital circuits. It is usually performed as a preprocessing step before ATPG starts, and the results obtained will facilitate ATPG to complete faster. [0003] Backt...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/33G06F30/333G06F30/34
CPCG06F30/33G06F30/333G06F30/34
Inventor 赖李洋林晓泽梁华潇梁海成
Owner SHANTOU UNIV
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