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Processor based on RSIC-V Hash algorithm

A hash algorithm and processor technology, applied in the direction of electrical digital data processing, digital data processing components, instruments, etc., can solve the problems of large area and inability to apply precision instrument data processing, etc., to achieve chip area saving, high performance and efficiency effect

Pending Publication Date: 2022-01-14
厘壮信息科技(苏州)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, the area occupied by the existing hash algorithm processor is too large, resulting in the dilemma that it cannot be applied to precision instruments for data processing

Method used

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  • Processor based on RSIC-V Hash algorithm
  • Processor based on RSIC-V Hash algorithm
  • Processor based on RSIC-V Hash algorithm

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0031] like figure 1 As shown, a processor based on the RSIC-V hash algorithm provided by this embodiment, the processor includes a central processing unit 1, a data pre-cache processor 2, a debugging unit 3, a decoder module 4, a general-purpose register module 5, Arithmetic logic unit module 6, state register module 7, load storage unit module 8, DIV module 9, first two-to-one selector module 10, second two-to-one selector module 11 and data integration two-to-one selector module 12 ;

[0032] General register module 5 includes rA data access port 5-1, rB data access port 5-2, w data access port 5-3, wD data access port 5-4, rDA data access port 5-5 and rDB data port 5 -6;

[0033] The arithmetic logic unit module 6 includes a first OpA data access port 6-1, a first OpB data access port 6-2, an Add data port 6-3, a first RD data port 6-4 and a logical operation instruction data port 6-5; the logic operation command data interface port 6-5 is connected to the central secon...

Embodiment 2

[0037] like figure 1 As shown, a processor based on the RSIC-V hash algorithm provided by this embodiment, the processor includes a central processing unit 1, a data pre-cache processor 2, a debugging unit 3, a decoder module 4, a general-purpose register module 5, Arithmetic logic unit module 6, state register module 7, load storage unit module 8, DIV module 9, first two-to-one selector module 10, second two-to-one selector module 11 and data integration two-to-one selector module 12 ;

[0038] General register module 5 includes rA data access port 5-1, rB data access port 5-2, w data access port 5-3, wD data access port 5-4, rDA data access port 5-5 and rDB data port 5 -6;

[0039] The arithmetic logic unit module 6 includes a first OpA data access port 6-1, a first OpB data access port 6-2, an Add data port 6-3, a first RD data port 6-4 and a logical operation instruction data port 6-5; the logic operation command data interface port 6-5 is connected to the central secon...

Embodiment 3

[0044] like figure 1 As shown, a processor based on the RSIC-V hash algorithm provided by this embodiment, the processor includes a central processing unit 1, a data pre-cache processor 2, a debugging unit 3, a decoder module 4, a general-purpose register module 5, Arithmetic logic unit module 6, state register module 7, load storage unit module 8, DIV module 9, first two-to-one selector module 10, second two-to-one selector module 11 and data integration two-to-one selector module 12 ;

[0045] General register module 5 includes rA data access port 5-1, rB data access port 5-2, w data access port 5-3, wD data access port 5-4, rDA data access port 5-5 and rDB data port 5 -6;

[0046] The arithmetic logic unit module 6 includes a first OpA data access port 6-1, a first OpB data access port 6-2, an Add data port 6-3, a first RD data port 6-4 and a logical operation instruction data port 6-5; the logic operation command data interface port 6-5 is connected to the central secon...

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Abstract

The invention provides a processor based on an RSIC-V hash algorithm. The processor comprises a central processing unit, a data pre-caching processing unit, a debugging unit, a decoder module, a general register module, an arithmetic logic unit module, a state register module, a load storage unit module, a DIV module, a first either-or selector module, a second either-or selector module and a data integration either-or selector module. The processor based on the RSIC-V Hash algorithm provided by the invention has the technical effects that data input into the processor based on the RSIC-V Hash algorithm can be subjected to different data processing frequencies on the basis of different internally set operation references to form an unsigned digital set Xn, then the arithmetic logic unit module for further performing fixed-point operation on the binary information performs logic operation on the data, thereby effectively avoiding noise occurring in the fixed-point operation process of the binary information caused by different types of input data.

Description

technical field [0001] The invention belongs to the technical field of processors, and in particular relates to a processor based on an RSIC-V hash algorithm. Background technique [0002] With the rapid development of wireless connections, big data, and artificial intelligence technologies, devices in the embedded field begin to have more perception capabilities and more flexible network connection functions. Judging from the development trend of applications, these devices not only require ultra-low power consumption, but also need to have more powerful data acquisition and processing capabilities. Compared with x86 and ARM architectures, RISC-V can be customized and optimized for different application fields at a lower cost. In recent years, it has become a research hotspot for domestic and foreign research institutions and enterprises. On the other hand, artificial intelligence, as the most popular science and technology today, has penetrated into all walks of life and ...

Claims

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Application Information

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IPC IPC(8): G06F7/57
CPCG06F7/57
Inventor 蔡斌王坤李斌徐培欣冯波
Owner 厘壮信息科技(苏州)有限公司