FPGA (Field Programmable Gate Array) hardware architecture, data processing method thereof and storage medium

Abstract

The invention relates to an FPGA (Field Programmable Gate Array) hardware architecture, a data processing method and device, computer equipment and a storage medium. The method comprises the following steps: acquiring to-be-processed first picture feature data; and inputting the first picture feature data into a pedestrian re-identification network model to obtain classification identification information. A structural block of the pedestrian re-identification network model comprises a forward hierarchical connection group, a backward hierarchical connection group and a channel scale selection module which are connected in sequence, and each of the forward hierarchical connection group and the backward hierarchical connection group comprises a plurality of first structural units. The first structure unit comprises a first 1 * 1 convolutional network, a first batch standardization network, a first translation network, a second 1 * 1 convolutional network, a second batch standardization network and a linear activation function network which are connected in sequence, and the channel scale selection module comprises a summation unit. According to the method, the data processing method realized by neural network acceleration of an FPGA (Field Programmable Gate Array) hardware architecture can be optimized.

Description

technical field [0001] The present application relates to the technical field of FPGA hardware processing, in particular to an FPGA hardware architecture and a data processing method, device, computer equipment and storage medium. Background technique [0002] The current FPGA-based neural network acceleration hardware architecture mainly focuses on improving the following performances: FPGA (Field Programmable Gate Array, Field Programmable Gate Array) computing power, network accuracy, and network model size. The FPGA hardware architecture almost includes on-chip cache, convolution acceleration module, pool (pooling) module, load (loading) module, save (storage) module, and instruction control module. The FPGA hardware architecture is not too difficult to implement, but the software compilation is relatively difficult to implement. [0003] Software compilation needs to adapt to different network models and be compatible with changes in FPGA hardware. At the same time, it...

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Problems solved by technology

In addition, there are various network models and many open source network model platforms, which lead to the diversification of FPGA hardware architecture.

[0004] It can be seen from the above that due to the coordination problem of software and hardware, when using the FPGA hardware architecture to realize the accelerated processing of image data by the neural network, if the software settings are more complicated, the FPGA hardware architecture will also be more complicated based on the software settings.

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