Shortest path acquisition method and device based on memristor pulse coupling neural network

Abstract

The invention discloses a shortest path acquisition method and device based on a memristor pulse coupling neural network, and the method comprises the steps: directly mapping edges and vertexes of a weighted graph to synapses and neurons on the memristor-based pulse coupling neural network, recording the activation time of the neurons and the connectivity of the given neurons, and obtaining the shortest path from the starting neuron to all other neurons through highly parallel pulse propagation. According to the pulse coupling neural network based on the memristor, high parallelism of physical characteristics of the memristor is fully utilized, and the shortest path is obtained with low time complexity and space complexity; and 100% path optimality is obtained in the eight-vertex weighted graph, and the energy consumption is as low as 0.33 [mu]J.

Description

technical field [0001] The invention relates to the technical field of non-volatile memory, in particular to a method and device for obtaining the shortest path based on a memristor pulse-coupled neural network, which is applied to solving the shortest path problem in graph calculation. Background technique [0002] Graph is an important data structure that can fully express the connection and dependency attributes of things in nature, so graph computing is widely used in the computer field. The shortest path problem is a classic problem in graph computing, which is to find a shortest path between the vertices of a given graph. Many problems can be efficiently solved by the shortest path method, such as path planning, signal pathway, drug development, etc. Traditional algorithms for solving the shortest path problem, such as Dijkstra's algorithm, use complex data structures, Floyd's algorithm, and have high time complexity Moreover, these two classic algorithms are execut...

AI Technical Summary

Problems solved by technology

However, the von Neumann machine executes instructions sequentially, which does not match the parallelism of the pulse-coupled neural network algorithm

Although the ASICs of pulse-coupled neural networks based on traditional silicon-based semiconductor technology have small chip area and low energy consumption, there is still a lack of a new type of device-based pulse-coupled neural network hardware.

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