Parallel processing method and system for single fine granularity in capacitance extraction by random walk

Abstract

The invention relates to the technical field of integrated circuit computer aided design, and concretely relates to a parallel processing method and system for single fine granularity in capacitance extraction of random walk. The method comprises the following steps: obtaining interconnection line information, and cooperating with a process file to obtain a physical three-dimensional structure of an integrated circuit; configuring a plurality of threads and the converging precision according to user requirements and the number of processor operation cores; constructing a closed and wrapped Gaussian surface for each conductor; calculating probability density according to the area of the Gaussian surface; selecting a plurality of points from the Gaussian surface according to the probability density; putting the selected points into an operation queue as a single operation unit; enabling each thread to sequentially extract points on the Gaussian surface from the operation queue to execute random walk, and if the random walk reaches the surface of the conductor or the boundary, completing one-time random walk, and storing a random walk result until the operation queue is empty; and if the random walk result reaches convergence precision, stopping capacitance extraction, and outputting an extraction result. The method is high in parallelism and high in expansibility.

Description

technical field [0001] The invention relates to the technical field of computer-aided design of integrated circuits, in particular to a single fine-grained parallel processing method and system for random walk in capacitance extraction. Background technique [0002] The process of integrated circuit design generally first divides software and hardware, and basically divides the design into two parts: chip hardware design and software collaborative design. Among them, chip hardware design includes: 1. Functional design stage; 2. Design description and behavior-level verification; 3. Logic synthesis; 4. Physical design verification; 5. Layout and wiring. In physical design verification, an important link is called parasitic parameter extraction. In order to improve the calculation accuracy, it is necessary to perform more accurate extraction calculations on parameters such as inductance and capacitance. The random walk capacitance extraction algorithm can provide accurate ext...

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Problems solved by technology

[0005] Aiming at the defects existing in the prior art, the object of the present invention is to provide a single fine-grained parallel processing method and system for random walk in capacitance extraction, which solves the problem that the existing random walk parallel processing method cannot take into account both accuracy and high efficiency. question

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