Parasitic capacitance test structure and method of FinFET

Abstract

The invention discloses a parasitic capacitance test structure of a FinFET. The FinFET comprises a gate structure, a lightly doped source region and a lightly doped drain region which are formed by a first conductive type lightly doped region, a side wall, a source region and a drain region which are formed by a first conductive type heavily doped region, a second conductive type well region and a body lead-out region which is formed by a second conductive type heavily doped region. The number of the parasitic capacitance test structures of the FinFET is multiple, and first conductive type well regions are formed in fin bodies in forming areas of the multiple parasitic capacitance testing structures. A first test structure in the parasitic capacitance test structure is formed by replacing the second conductive type well regions of the FinFET with first conductive type well regions and removing thelightly doped source region and the lightly doped drain region at the same time. The invention also discloses a parasitic capacitance test method of the FinFET. Butterfly defects can be prevented, mass production can be facilitated, and calculation of stray capacitance of the zeroth metal layer and the zeroth through hole and the electrical thickness of the gate dielectric layer can be conveniently achieved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a FinFET parasitic capacitance testing structure. The invention also relates to a method for testing the parasitic capacitance of the FinFET. Background technique [0002] The gate structure of FinFET usually adopts a metal gate (MG), and the gate dielectric layer usually includes a high dielectric constant layer (HK). The electrical thickness of the gate dielectric layer usually needs to be tested and extracted through the capacitance of the gate. Such as figure 1 As shown, it is a schematic structural diagram of the existing FinFET; the existing FinFET includes: the FinFET includes a gate structure, a lightly doped source region and a shallowly doped drain region composed of a lightly doped region of the first conductivity type, sidewalls 110, and A source region 105 and a drain region 106 composed of a heavily doped region of the first conductivi...

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Problems solved by technology

[0012] However, in actual production, since the second test structure only removes M0 and V0, it passes through the dielectric layer during the test and is directly connected to the source or drain region, that is, S / D, so the parasitic capacitance value of M0 or V0 cannot be measured. , so it is necessary to combine the test structure of the first test structure to obtain the parasitic capacitances of M0 and V0

[0013] but Figure 2A A large metal gate grows on the large-area shallow trench isolation structure 104b, and the dishing phenomenon of the shallow trench isolation structure 104b and the metal gate is prone to occur, resulting in defects, which is not conducive to mass production.

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