[0051] The following detailed description will be described below with reference to the accompanying drawings and examples. It will be appreciated that the specific embodiments described herein are only used to explain the relevant invention, not the limitation of the invention. Further, in order to facilitate the description, only portions associated with the relevant invention are shown in the drawings.
[0052] It should be noted that the structures, proportions, sizes, and the like shown in the drawings are used only for the contents described in the specification to provide understanding and reading of those skilled in the art, not to limit the disclosure of this disclosure. The conditions are limited, so that there is no technical substantive significance, the modification of any structure, the ratio relationship or the adjustment of the size, and the effects of the effects that do not affect the efficacy and the purpose of the present disclosure, should still fall in this disclosure The disclosed technical content can be covered. At the same time, the use of "upper", "first", "second" and "one", which are referenced in this specification are only clear, not to limit the scope of the present disclosure, The change or adjustment of the relative relationship is also considered to be implemented by the present disclosure as the present disclosure.
[0053] It should be readily understood that the meaning of "in ..." on ... "" and "above" in the present disclosure should be explained in the broadest manner, so that "on ... Not only means "directly in something", but also means including "in something" in some cases between the intermediate components or layers between the two.
[0054] In addition, in order to facilitate the description, it may be used in this disclosure, such as "below", "under ...", "lower", "above", "upper", etc. Describe the relationship between one element or component and another element or component shown in the drawings. In addition to the orientation described in the figure, space relative terms are also intended to cover different orientations in use or operation. The device can be oriented in other ways (rotated 90 ° or other orientation), and the space used in the present disclosure relative description can be explained in the same manner.
[0055] In addition, in the case of an incapable, the features and features in the present disclosure can be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings.
[0056] figure 1 It is a schematic structural view of a semiconductor package structure according to an embodiment of the present disclosure. like figure 1As shown, the semiconductor package structure includes a first chip 1, a second chip 2, a bridging chip 3, a retraining line 4, a third conductive post 5, a first mold sealing layer 6, a second mold sealing layer 7, a bottom filler? 8 and external electrical connector 9. Wherein, the second chip 2 can be disposed adjacent to the first chip 1. The bridging chip 3 can be electrically connected to the first chip 1 and the second chip 2. The first chip 1 and the second chip 2 can be electrically connected to the bridged chip 3 by the retrail line 4. The bottom filler 8 can be coated with the bottom of the first chip 1, the bottom of the second chip 2, and the bottom of the bridge chip 3. The first mold sealing layer 6 can cover the third conductive post 5 and the bridge chip 3. The second mold sealing layer 7 can cover the first chip 1 and the second chip 2.
[0057] In the present embodiment, the first chip 1 and the second chip 2 may be a chip of various functions, and the first chip 1 may, for example, a high bandwidwidth Memory (HBM) chip. The second chip 2 can be, for example, an Application Specific Integrated Circuit (ASIC) chip.
[0058] In the present embodiment, the bridging chip 3 can include a vertical conductive path 31. The vertical conductive path 31 may not only provide a signal interconnect path between the first chip 1 and the second chip 2, but the vertical conductive path 31 may be between the first chip 1 and / or the second chip 2 Provides a conductive path. The vertical conductive path 31 can include a first conductive post 311, a second conductive post 313, and a bridge retaining layer 312. The first conductive column 311 can be electrically connected to the second conductive post 313 through the bridge weight wiring layer 312. The third conductive post 5 can be disposed adjacent to the bridge chip 3, and the height of the first conductive post 311 can be smaller than the height of the third conductive post 5.
[0059] The external power supply may be powered by the third conductive column 5 and the retraining line 4 as the first chip 1 and the second chip 2 (first conductive path), or the vertical conductive path 31 and heavy in the bridge chip 3 may be selected. The wiring layer 4 is a first chip 1 and a second chip 2 supply (second conductive path), and the second power supply path relative to the first conductive path is shorter.
[0060] In a scenario, such as figure 1 In the figure in the figure, the center of the first conductive post 311 of the bridge chip 3 can be located on the same vertical line. In another scene, such as figure 1 In the figure (b), the center of the bridge chip 3 and the center of the second conductive post 313 can be located on different vertical lines.
[0061] In the present embodiment, the bridging chip 3 can include a plastic package material. The plastic package material can be epoxy molding compound (EMC). Epoxy molding can include epoxy resins and fillers. The filler can be, for example, silica (silicon fine powder). Plastic packaging materials can reduce insertion loss compared to semiconductor materials such as silicon. In practice, in high frequency 70 GHz, the insertion loss of the plastic package material of the semiconductor material can be four times that of the plastic package material. Specifically, such as figure 1 In the figure in the figure, the plastic package material included in the bridge chip 3 may be a first plastic package material 32. like figure 1 In the figure in the figure, the plastic package material included in the bridging chip 3 may include a first plastic package material 32 and a second plastic package material 33.
[0062] In this embodiment, if figure 1 In the figure in the figure, the diameter of the second conductive post 313 is tapered in the direction of the bridge chip 3 toward the retaining line 4. The side wall of the second conductive column 313 is a curved surface. In the process, the second conductive column 313 of the larger diameter can be directly formed using a photolithography technique, thereby increasing the power transmission capacity.
[0063] In the present embodiment, the outer electrical connector 9 may, for example, be a solder ball, a ball grid array (BGA), a controlled collapse chip connection, a C4) bump or microbar.
[0064] The semiconductor package structure provided by the present disclosure, the bridging chip can be produced by THRough Moldvia, TMV. In addition, the photolithography can directly form a larger diameter conductive column, thereby increasing the power transmission capacity.
[0065] Figures 2 to 6 The structural diagram of the first manufacturing process of the bridge chip 3 according to the embodiment of the present disclosure.
[0066] Please refer to figure 2 In the first panel 10, a first conductive post 311 is formed to form a first plastic package material 32 that covers the first conductive post 311, and the first plastic package material 32 is thinned to expose the first conductive post 311.
[0067] Please refer to image 3 Further, a bridging wiring layer 312 is formed on the first plastic package material 32.
[0068] Please refer to Figure 4 The second conductive column 313 and the interconnect structure 34 are formed on the bridging retaining line 312.
[0069] Here, the first conductive column 311 and the second conductive post 313 may be directly formed by photolithography techniques.
[0070] Please refer to Figure 5 Further, a second plastic package material 33 having a second conductive post 313 is formed.
[0071] Please refer to Image 6 The second plastic package material 33 is thinned to expose the second conductive post 313.
[0072] Here, the thin process can be, for example, a grinding or a chemical mechanical polishing, CMP process.
[0073] Figure 7 to 11 It is a schematic structural diagram of the second manufacturing process of the bridge chip 3 according to the present disclosure.
[0074] Please refer to Figure 7 The second conductive post 313 is formed on the first carrier plate 10 to form a second plastic package material 33 covering the second conductive post 313, and the second plastic package material 33 is thinned to expose the second conductive post 313.
[0075] Please refer to Figure 8 The bridging wiring layer 312 is formed on the second plastic package material 33.
[0076] Here, the process can be used in the process, and the present disclosure is not specifically defined by this disclosure, for example, including but not limited to lithography, plating, electrocholastic plating (ElectrolesSplating). Bridge returns wiring 312.
[0077] Please refer to Figure 9 The first conductive post 311 and the interconnect structure 34 are formed on the bridging retaining line 312.
[0078] Please refer to Figure 10 Further, a first plastic package material 32 that covers the first conductive post 311 is formed.
[0079] Please refer to Figure 11 Thin, the first plastic package material 32 is thinned to expose the first conductive post 311.
[0080] Figure 12 to 16 It is a schematic structural diagram of the manufacturing process of the semiconductor package structure according to the embodiment of the present disclosure.
[0081] Please refer to Figure 12 The third conductive column 5 is provided on the second carrier 11.
[0082] Please refer to Figure 13 , The bridging chip 3 is provided on the second carrier 11. The bottom filler 8 of the bottom portion of the bridge chip 3 is formed.
[0083] The bridge chip 3 here can be Figure 4 or Image 6 or Figure 9 or Figure 11 The bridged chip 3 shown.
[0084] Please refer to Figure 14 The first mold sealing layer 6 covering the third conductive post 5 and the bridging chip 3 is formed, and the first mold sealing layer 6 is thinned.
[0085] Please refer to Figure 15 The retaining layer 4 is formed on the first mold sealing layer 6. A first chip 1 and the second chip 2 are provided on the retain line 4. A bottom filler 8 having a bottom portion of the first chip 1 and the bottom of the second chip 2 is formed separately. The second mold sealing layer 7 that is covered with the first chip 1 and the second chip 2 is formed.
[0086] Please refer to Figure 16 To form an external connector.
[0087] The method of manufacturing a semiconductor package structure in this embodiment can realize similar technical effects similar to the aforementioned semiconductor package structure, and details are not described herein again.
[0088] Although the present disclosure is described and illustrated in reference to the present disclosure, these descriptions and description are not limited to the disclosure. Those skilled in the art can clearly understand that various changes can be made, and can be replaced in the embodiment without departing from the spirit and scope of the present disclosure as defined by the appended claims. The illustration may not be drawn to scale. It is due to variables in the manufacturing process, the like, and there may be differences between the techniques reproduction between the present disclosure and the actual equipment. Other embodiments of the present disclosure that are not particularly described may be present. The instructions and patterns should be considered as illustrative, not restrictive. Modifications can be made to adapt specificities, materials, substances, methods or processes to the objectives, spirit, and scope of the present disclosure. All such modifications have fallen within the scope of the appended claims. Although the method disclosed in the present disclosure is described with reference to a particular operation performed in a particular order, it is understood that these operations can be combined, subdivided or re-sorted without departing from the teachings of the present disclosure. Therefore, the order and packet of the operation will not be limited to the present disclosure unless specifically indicated in the present disclosure.
