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Centralized control method and system for interconnection among multiple FPGA chips

A centralized control and control system technology, applied in the field of communication, can solve problems such as low speed, difficult to meet complex system control requirements, difficult to meet control timing requirements, etc., to achieve the effect of increasing line speed

Pending Publication Date: 2022-02-18
四川恒湾科技有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Distributed control means that each FPGA is controlled individually. The disadvantage of this is that it is difficult to meet the control timing requirements for the control of timing requirements between multiple FPGAs.
Therefore, centralized control is the preferred control method, and centralized control usually uses a switch (Ethernet switch chip) chip, such as image 3 As shown, the PS (control system / processing system) controls the PS of other FPAGs through the switch chip. This method has a low rate and is difficult to meet the control requirements of complex systems.

Method used

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  • Centralized control method and system for interconnection among multiple FPGA chips
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  • Centralized control method and system for interconnection among multiple FPGA chips

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specific Embodiment approach

[0031] see figure 1 , figure 2 and Figure 4 , a centralized control method for the interconnection of multiple FPGA chips provided by the embodiment of the present application. The present invention proposes a high-speed centralized control method based on the interconnection of programmable logic devices in the processor. The principle is to use the main The programmable logic device of processor 1 (hereinafter referred to as PL) uniformly configures the programmable logic device of slave processor 2, and the original control system of slave processor 2 (control system hereinafter referred to as PS) is only used for system initialization Some initialization configurations, thereby increasing the line speed, and satisfying the complex control and management of the system of massive antenna technology (Massive MIMO system), the line rate can reach 4GHz. Its specific implementation is as follows:

[0032]The hardware of the present invention is all based on the Xilinx ZYNQ...

Embodiment 2

[0053] see Figure 5 , a centralized control system interconnected among multiple FPGA chips, including:

[0054] The processor module 3 is used for the main processor 1 and multiple slave processors 2 centrally controlled by the main processor 1; the initialization module 4 is used for controlling the control system of the main processor 1 and multiple slave processors 2 The system performs an initialization operation; the configuration module 5 is used for the control system of the main processor 1 to send management and configuration commands to the programmable logic device of the main processor 1 through the AXI bus; the inter-chip interaction module 6 is used for the main processor 1 After receiving the management and configuration commands, the programmable logic device converts the management and configuration commands into port physical layer data through the chip2chip protocol, and performs data interaction with multiple slave processors 2 respectively.

Embodiment 3

[0056] see Figure 4 , an electronic device comprising a main processor 1, a plurality of slave processors 2 connected to the main processor 1, at least one memory and a data bus; wherein: the main processor 1, a plurality of slave processors 2, and the memory through The data bus completes mutual communication; the memory stores program instructions that can be executed by the processor, and the master processor 1 and multiple slave processors 2 call the program instructions to execute a centralized control method for interconnecting multiple FPGA chips. Example implementation:

[0057] The main processor 1 and multiple slave processors 2 centrally controlled by the main processor 1; the control system of the main processor 1 and the control systems of multiple slave processors 2 are initialized; the control system of the main processor 1 passes The AXI bus sends management and configuration commands to the programmable logic device of the main processor 1; after receiving t...

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Abstract

The invention provides a centralized control method for interconnection among multiple FPGA chips, and relates to the technical field of communication. A master processor and a plurality of slave processors controlled by the master processor in a centralized manner are included. the control system of the master processor and the control systems of the plurality of slave processors are initialized; the control system of the master processor sends management and configuration commands to a programmable logic device of the master processor through an AXI bus; and after receiving a management and configuration command, the programmable logic device of the master processor converts the management and configuration command into port physical layer data through a chip2chip protocol, and performs data interaction with the programmable logic devices of the plurality of slave processors respectively. Therefore, the linear speed of transmission can be improved, and complex control and management of a large-scale antenna technology system can be met.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a centralized control method and system for interconnecting multiple FPGA chips. Background technique [0002] 5G NR (New Radio) is a global 5G standard based on a new air interface design based on OFDM (Orthogonal Frequency Division Multiplexing). It is also an important next-generation cellular mobile technology. A key technology of 5G is large-scale Antenna technology, namely Massive MIMO. The number of antennas in a traditional TDD (Time Division Duplexing) network is usually 2, 4, or 8 antennas, while the number of channels in MassiveMIMO can reach 64 antennas. As the number of antennas increases, the system capacity will increase exponentially, but correspondingly, the complexity of system implementation will also increase exponentially. Therefore, the logic implementation of a Massive MIMO system usually requires multiple FPGAs to complete. In order to realize the...

Claims

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Application Information

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IPC IPC(8): G06F15/177G06F15/163G06F9/445G06F1/24
CPCG06F15/177G06F15/163G06F9/4451G06F1/24
Inventor 张英静
Owner 四川恒湾科技有限公司
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