Integrated circuit mask layout, pattern correction method and mask thereof

Abstract

The invention discloses a mask layout of an integrated circuit. The mask layout comprises a plurality of active region patterns and a plurality of sealing ring patterns; the active region pattern is parallel to the horizontal direction of the mask layout; an included angle is formed between the sealing ring pattern and the horizontal direction of the mask layout; a plurality of active region patterns form a group, and a plurality of groups of active region patterns are formed in total; each group of active region patterns corresponds to the adjacent alignment mark, and the edge of one side, close to the sealing ring pattern, of each active region pattern in the same group of active region patterns is flush in the vertical direction of the mask layout. Compared with the prior art, the mask layout and the mask manufactured by adopting the layout provided by the invention have the advantage that a better process window can be obtained in the manufacturing process of an integrated circuit.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to an integrated circuit mask layout, a pattern correction method and a mask. Background technique [0002] In the manufacturing process of semiconductor integrated circuits, optical proximity correction (Optical Proximity Correct, OPC for short) needs to be performed on the design layout, so as to improve the manufacturability of graphics. OPC is to improve the impact of optical proximity effect on exposure, so the basic work is to cut and move the layout segment by line, and then iterate continuously, and finally verify with the actual results. [0003] In the manufacturing process of Fin Field Effect Transistor (FinFet), there is a layout of a mask, such as figure 1 As shown, the active area (CAA) of the mandrel structure and the 45-degree sealing ring (seal ring) keep a fixed distance, so that the active area (CAA) and the overhang of the ...

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Problems solved by technology

[0003] In the manufacturing process of Fin Field Effect Transistor (FinFet), there is a layout of a mask, such as figure 1 As shown, the active area (CAA) of the mandrel structure and the 45-degree sealing ring (seal ring) keep a fixed distance, so that the active area (CAA) and the overhang of the alignment mark AA are not same, resulting in the inability to obtain the ideal process window

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