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Clock loss monitoring circuit and implementation method

A technology for monitoring circuits and implementation methods, applied in fault hardware testing methods, electrical digital data processing, error detection/correction, etc., can solve the problems of high complexity and high cost, and achieve fast response speed, low cost, and high security. Effect

Active Publication Date: 2022-02-25
NANJING SEMIDRIVE TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

To monitor the loss of all clocks in the traditional way, the cost is high and the complexity is high

Method used

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  • Clock loss monitoring circuit and implementation method
  • Clock loss monitoring circuit and implementation method
  • Clock loss monitoring circuit and implementation method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0037] figure 1 For the clock loss monitoring circuit diagram according to the present invention, such as figure 1 As shown, the clock loss monitoring circuit of the present invention includes a delay element, an inverter, an AND gate, a register with an asynchronous reset terminal and a clock detection register, wherein the delay element is connected with the inverter, and the The inverter is connected with the AND gate, the AND gate is connected with the register with asynchronous reset terminal, and the register with asynchronous reset terminal is connected with the clock detection register.

[0038] The delay element is used to generate an asynchronous reset signal with an asynchronous reset terminal register and output it to the register with an asynchronous reset terminal when the rising edge of the reference clock passes through the delay element, and reset the register with an asynchronous reset terminal to 0 .

[0039] The register with an asynchronous reset termina...

Embodiment 2

[0049] figure 2 For the implementation method flowchart of the clock loss monitoring circuit according to the present invention, reference will be made below figure 2 , the implementation method of the clock loss monitoring circuit of the present invention is described in detail.

[0050] In step 201, when the rising edge of the reference clock passes through the delay element, an asynchronous reset signal of the register is generated to reset the register to 0.

[0051] Preferably, the rising edge of the reference clock is reversed after passing through the delay element, and the delayed and reversed reference clock signal is logically ANDed with the reference clock signal to generate an asynchronous reset signal of the register.

[0052] In step 202, when the rising edge of the monitored clock arrives, the register is assigned a value of 1.

[0053] In step 203, the value of the register is checked at the falling edge of the reference clock, and an interrupt is output if...

Embodiment 3

[0056] Such as image 3As shown, in the embodiment of the present invention, according to the Nyquist sampling law, half of the clk_base (high level) is more than twice slower than clk_check, and after half a clock cycle, the rising edge turns into a falling edge. As long as the delay time satisfies the minimum reset pulse width of DFF (Data flip-flop, data flip-flop), from a logical perspective, the delay time should be as small as possible, one level of buffer or one delay cell can be used. The asynchronous reset of DFF will reset active_ind to the reset value.

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Abstract

A clock loss monitoring circuit comprises a time delay element, a phase inverter, an AND gate, a register with an asynchronous reset end and a clock detection register, the time delay element is connected with the phase inverter, the phase inverter is connected with the AND gate, the AND gate is connected with the register with the asynchronous reset end, the register with the asynchronous reset end is connected with the clock detection register; and the clock detection register is used for receiving the inverted reference clock signal and the to-be-monitored signal output by the register with the asynchronous reset end, and checking the value of the register at the falling edge of the reference clock. According to the clock loss monitoring circuit and the implementation method, the cost can be reduced, and the response speed is high.

Description

technical field [0001] The invention relates to the field of chip technology, in particular to a clock loss monitoring circuit and an implementation method. Background technique [0002] In the prior art, among chips with functional safety requirements, periodic signals such as clocks have correctness and security requirements, and it is necessary to monitor whether the clock is lost during system operation. [0003] The traditional method of monitoring whether the clock is lost, one method is to send the clock signal to the outside of the chip for observation, and the other method is to use different clocks for counting, and periodically compare whether the value of the counter has changed, thereby indirectly Determine whether the clock is lost. [0004] In a common chip system, there are many different clocks sent to different modules. To monitor the loss of all clocks in a traditional way has high cost and high complexity. Contents of the invention [0005] In order ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/14G06F11/22
CPCG06F1/14G06F11/2273G06F11/2205
Inventor 顾雪春张力航
Owner NANJING SEMIDRIVE TECH CO LTD