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Simplified grooving design method for high-voltage DMOS

A design method and high-voltage technology, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problem of low utilization rate of chips, and achieve the effect of avoiding lithography overlay deviation, simplifying the process, and reducing environmental pollution

Pending Publication Date: 2022-03-18
厦门吉顺芯微电子有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] figure 1 As shown, it is a cross-sectional view of a conventional MOSFET process, and it can be seen that figure 1 low chip utilization

Method used

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  • Simplified grooving design method for high-voltage DMOS
  • Simplified grooving design method for high-voltage DMOS

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Embodiment Construction

[0012] The technical solution of the present invention will be specifically described below in conjunction with the accompanying drawings.

[0013] A high-voltage DMOS simplified trench design method of the present invention adopts a trench design in the Cell area to optimize the longitudinal structure. The trench design is realized through self-alignment and Hard Mask technology under the premise of solving the latch effect , in order to reduce processing steps and avoid lithography alignment deviation.

[0014] A kind of high-pressure DMOS simplified digging design method of the present invention, concrete realization steps are as follows:

[0015] Step 1. Use conventional technology to complete the processing of functional areas such as RIN, P well (P- area), Source (N+, area) on N-type EPI;

[0016] Step 2. After P+ implantation and doping, use the self-alignment process to dig grooves on the product so that N+ / P+ is connected to Metal;

[0017] Step 3: Treat the surface...

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Abstract

The invention relates to a high-voltage DMOS simplified grooving design method. According to the method, in a Cell region, a grooving design is adopted, a longitudinal structure is optimized, and the grooving design is realized through self-alignment and Hard Mask processes on the premise of solving a latch-up effect, so that processing steps are reduced, and photoetching alignment deviation is avoided. According to the method, after the grooving design is adopted, under the condition that parameters are not changed, the cost is saved, and the competitiveness of products is improved.

Description

technical field [0001] The invention relates to the structure of a Cell region of a high-voltage MOSFET device, belongs to the field of combining high-voltage MOSFET and low-voltage MOSFET technologies, and in particular relates to a high-voltage DMOS simplified trenching design method. Background technique [0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), referred to as DMOS transistor, is a product widely used in various power circuit devices. [0003] At present, the market has higher and higher requirements for the cost performance of MOSFET products. In the case of constant or improved device performance, the chip area should be reduced as much as possible, the utilization rate of the chip should be improved, the processing steps should be reduced, the alignment deviation of lithography should be avoided, and the cost should be reduced. reduce environmental pollution. [0004] figure 1 As shown, it is a cross-sectional view of a conventional MOSFET ...

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Application Information

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IPC IPC(8): H01L21/336H01L29/06
CPCH01L29/66712H01L29/0684
Inventor 郝让峰
Owner 厦门吉顺芯微电子有限公司