Three-dimensional chip testing method, device and system

Abstract

The invention provides a three-dimensional chip testing method, device and system. The test method comprises the steps that a power supply device applies a detection signal to a to-be-detected port of the three-dimensional chip, an electric signal of the power supply device and / or a feedback signal of the to-be-detected port are / is detected, the feedback signal is an electric signal generated after a to-be-detected line receives the detection signal, and the to-be-detected port is detected according to the detected electric signal and / or the feedback signal. And determining whether the three-dimensional chip has a short-circuit fault or not. According to the method, under the condition that an ATE machine is not adopted, whether the three-dimensional chip has a fault or not can be determined according to the detected result by detecting the electric signal of the power supply equipment and / or the feedback signal of the port to be detected, electrical performance testing after 3D IC packaging is achieved, and therefore the testing cost of the 3D IC is reduced, and the testing efficiency of the 3D IC is improved. Therefore, a problem of high cost of a test mode of short circuit or electric leakage of the 3D IC in the prior art is solved.

Description

technical field [0001] The present application relates to the field of semiconductors, in particular, to a testing method, device and system for a three-dimensional chip. Background technique [0002] Often, chips with normal functions will have problems of short circuit or electric leakage in some chips after the packaging process. 3DIC is a technology that connects logic chips and memory chips through hybrid bonding (hybrid bonding) technology to achieve near-memory computing. The technology is mainly composed of three parts, logic chip, memory chip and connection layer. Because it contains both logic chips and memory chips inside, the probability of short circuit and leakage after packaging process is higher than that of a single logic chip or memory chip. [0003] The current method used to test packaged chips, such as figure 1 As shown, professionals write corresponding test stimuli, and then use the ATE (Automatic Test Equipment) machine to deliver test stimuli to t...

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Problems solved by technology

[0006] The main purpose of this application is to provide a test method, device and system for a three-dimensional chip, to solve the problem of high cost of test methods for short circuit or leakage of 3D IC in the prior art

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