Packaging method of heterogeneous coplanar integrated chip

Abstract

The invention relates to a method for packaging a heterogeneous coplanar integrated chip, which comprises the following steps of: bonding and fixing the front surfaces (bonding pad surfaces) of various bare chips made of different materials and manufactured by different processes on the front surface of a glass substrate by using temporary bonding glue, arranging the chips according to a certain rule, pasting a blue film on the back surface of the glass substrate, and packaging the chips on the back surface of the glass substrate. Processing is carried out through a grinding machine or a thinning machine, technological parameters are optimized, coplanar thinning to the target thickness is achieved, and then discrete chips with the consistent thickness are obtained through de-bonding. Discrete chips are pasted on a high-heat-conduction shell, then coplanar ball planting is carried out, and the heterogeneous coplanar integrated chip is formed by welding the discrete chips at bonding pads corresponding to a multi-layer wiring substrate through an FC flip-chip bonding technology. The method has the advantages of being suitable for research and development of multi-variety and small-batch products, high in automation degree, low in cost and the like, and important technical support can be provided for subsequent miniaturization development of a three-dimensional heterogeneous integrated system.

Description

technical field [0001] The invention relates to a packaging method for heterogeneous coplanar integrated chips, especially a method for preparing heterogeneous coplanar integrated chips with multi-variety and small-batch product characteristics, which can realize flexible imposition, and can be used for the development of subsequent three-dimensional heterogeneous integrated packaging Provide important technical support. Background technique [0002] With the development of miniaturization of integrated circuits, two-dimensional integration technology can no longer meet the needs of future applications, and is gradually turning to three-dimensional integration technology. However, the high R&D cost makes the development of 3D integration technology slow, and the redevelopment of chips and remodeling of process lines will cost huge resources. To reduce research and development costs, Chinese Patent Publication No. CN111564429A, published on August 21, 2020, titled "A Three-d...

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Problems solved by technology

However, the high R&D cost makes the development of 3D integration technology slow, and the redevelopment of chips and remodeling of process lines will cost huge resources

To reduce research and development costs, Chinese Patent Publication No. CN111564429A, published on August 21, 2020, titled "A Three-dimensional Integrated Circuit Heterogeneous Integrated Chip and Packaging Method", discloses the use of temporary bonding, thinning, and through-hole wiring The method of integrating different IC devices with other processes, which uses two auxiliary substrates to achieve heterogeneous integration, although it is feasible, has the disadvantage that the auxiliary substrate on the temporary bonding surface is not a whole, and subsequent processing The process is not removed, and the total thickness is increased; another auxiliary substrate and a temporary bonding layer are added, and finally transferred to the final substrate layer, and the process is more complicated; high cost

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