Fractional frequency division and dynamic phase shift system based on PLL (Phase Locked Loop) circuit

Abstract

The invention provides a fractional frequency division and dynamic phase shift system based on a PLL circuit, and relates to the technical field of integrated circuits. Under the control of a first control signal, each clock selection module in the timer selects an ith clock signal, an ith clock signal, an (i-1) th clock signal, at least one forward shift signal, at least one backward shift signal and a reset signal according to the ith clock selection signal, the ith clock signal, the (i-1) th clock signal, the at least one forward shift signal and the at least one backward shift signal. And outputting the ith second control signal in the N second control signals and a shift signal corresponding to the ith clock selection module, so that the phase of the clock signal currently output by the PLL circuit is switched to the phase of the ith clock signal. According to the embodiment of the invention, the clock signal switching flexibility of the retimer can be improved, so that the frequency division clock signal output by the PLL is more accurate.

Description

technical field [0001] The present application relates to the technical field of integrated circuits, in particular to a fractional frequency division and dynamic phase shifting system based on a PLL circuit. Background technique [0002] At present, a phase-locked loop (PLL) is widely used in integrated circuits for processing clock signals. In many occasions, the output clock signal of the PLL needs not only a precise frequency, but also a strict phase requirement to complete the sampling work and minimize the bit error rate. In the PLL structure using a ring voltage-controlled oscillator (ringvco) with phase selection, the ring voltage-controlled oscillator can generally generate 6 to 16 output clocks with different phases, and the clocks with different phases are sent to the output frequency divider and passed through the phase Select the signal phase sel to select the output phase, and the output frequency is controlled by the integer frequency division signal div sel....

AI Technical Summary

Problems solved by technology

However, the retimer structure in the related art makes the flexibility of clock signal switching low, so that the precision of the frequency-divided clock signal output by the PLL is low

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