Signal shunting method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a signal shunting method and device, electronic equipment and a storage medium, and is applied to the technical field of segmentation verification of chip design, and the signal shunting method comprises the steps: obtaining a network flux diagram; determining a plurality of to-be-shunted target signals in the network flux diagram, wherein the to-be-shunted target signals are signals on the network whose weight is smaller than a first threshold value; partial signals in the target signals to be shunted are shunted to other redundant networks, the weight of the redundant networks is larger than a second threshold value, and the second threshold value is not smaller than the first threshold value. According to the method, the interconnection resources are dynamically subjected to transfer path configuration at the RTL level, and the signals possibly in the congestion network in the segmentation result are subjected to signal shunting processing such as transfer and dredging, so that the communication flow of each region can be improved in a balanced manner, the overall working frequency of the verification system is improved, the shunting processing is faster and more efficient, and the verification efficiency is improved. The segmentation and verification efficiency in the chip verification design is greatly improved.

Description

technical field [0001] The invention relates to the technical field of chip design segmentation verification, and in particular to a signal shunting method, device, electronic equipment and storage medium. Background technique [0002] When verifying the segmentation results of ultra-large-scale chip design, it is often necessary to use several pieces (such as dozens or even hundreds) of verification chips to form a verification system, and use IO pins between verification chips as the interconnection between segmentation signals resources, and thus interconnect resources are scarce resources in partition verification of large-scale chip designs. [0003] In the actual verification system, the IO resources between the verification chips need to be interconnected by physical wiring, such as figure 1 As shown, the signal a to signal d between the verification chip FPGA1 and the verification chip FPGA2 can be interconnected through the physical cable Cable_1. The time divisio...

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Problems solved by technology

[0004] Therefore, when the communication pressure of a certain Cable is too high, it will cause the verification chip to work at a lower operating frequency, that is, the operating frequency of the entire verification system may be affected by the communication pressure of the Cable and cannot meet the preset minimum operating frequency

[0005] For example, in the interconnection using TDM (Time Division Multiplexing), if the TDM Ratio (Time Division Multiplexing Ratio) is too large, the delay time will be too long, and the verification system cannot meet the minimum required operating frequency

[0006] For example, in the verification chip networking, the segmentation result formed by the segmentation algorithm may be unreasonable and limited by the physical resources of the verification system. Work at minimum operating frequency requirements

[0007] In order to meet the minimum operating frequency, it is necessary to re-segment, re-layout, and network the chip design. The segmentation and verification of large-scale chip designs are greatly restricted and cannot be carried out effectively, which affects the release of chips.

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