Power secondary equipment PCIe bus abnormal broken link self-recovery method and system

Abstract

The invention discloses an abnormal broken link self-recovery method and system for a PCIe (Peripheral Component Interconnect Express) bus of power secondary equipment. The method comprises the following steps of: 1, removing address space allocation information of a PCI (Peripheral Component Interconnect) core belonging to second PCIe equipment from bus route configuration information of a PCI controller on first PCIe equipment; 2, controlling a PCI controller on the first PCIe device to retrain the PCIe bus link, and if the PCIe bus link is recovered, executing the step 5; otherwise, executing the step 3; step 3, resetting and initializing the PCI core and the PCI controller; 4, controlling the PCI controller on the first PCIe equipment to retrain the PCIe bus link, waiting for the recovery of the PCIe bus link, and executing the step 5 after the recovery of the PCIe bus link; 5, address space allocation information belonging to the PCI core in the pre-stored PCIe bus configuration information is rewritten into the PCI core of the second PCIe equipment; and re-adding the address space allocation information belonging to the PCI core into the bus route configuration information of the PCI controller on the first PCIe equipment.

Description

technical field [0001] The invention belongs to the technical field of bus abnormality recovery, and in particular relates to a self-recovery method and system for PCIe bus abnormality disconnection of electric secondary equipment. Background technique [0002] PCIe (Peripheral Component Interconnect express) is a general-purpose bus specification that uses serial interconnection to transmit data in the form of point-to-point. Only one device can be connected to each end of a PCIe link, and the two devices are data sender and data receiver. In terms of transmission speed, PCIe version 1.0 is 2.5Gbps per channel in one direction, version 2.0 is 5Gbps, version 3.0 is 8Gbps, version 4.0 is 16Gbps, and the latest version 5.0 can reach 32Gbps. [0003] With the improvement of embedded system performance, PCIe bus technology has been more and more widely used in the embedded field. In power secondary equipment, PCIe bus is generally used to connect System On Chip (SOC, System On ...

AI Technical Summary

Problems solved by technology

[0005] 1. Adding an additional processor for link state recovery will increase the complexity of the design, add new hidden dangers to the system, and will greatly increase the cost of equipment;

[0006] 2. From the disconnection of the PCIe card to the completion of program reloading by the first processor, and then recovery of the link, if the system processor accesses the PCIe bus, the PCIe controller may not be able to respond to the read command of the system processor due to the disconnection , causing the system to freeze and the device to be abnormal;

[0007] 3. After the PCIe card is disconnected and the link training is completed again, the operating system needs to re-allocate resources such as address space for the PCIe device. If the allocated address is inconsistent with that before the disconnection, and the application program uses the bus address before the disconnection , the system may be abnormal due to access to the wrong address

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