13 results about "Bus routing" patented technology

The invention relates to an access request processing method, device and system and a chip. Comprising the following steps: receiving a data access request, and analyzing the data access request to obtain a target address requested to be accessed; determining an address field segment needing to be interleaved in the target address according to a preset interleaving granularity, the number of memories and the capacity of a single memory; interleaving the address field segment needing to be interleaved to obtain an interleaved address; sending the interleaved address to a bus routing module; and sending the interleaved address to the bus routing module to indicate the bus routing module to access the corresponding memory according to the interleaved address.

The invention relates to the technical field of artificial intelligence, and discloses a hybrid bonding-based large model reasoning data read-write method and system, a controller and a storage medium, and the method comprises the following steps: constructing hybrid bonding connection between a PIM chip and a DRAM chip and between the PIM chip and a FLASH chip; when the large model is used for reasoning, the weight of the large model is stored in the FLASH chip through the data bus, and the cue word of the large model is stored in the DRAM chip through the data bus; in the pre-filling stage, the PIM chip is used for respectively reading the weight and the cue word, and the calculated first key value is cached and written into the DRAM chip; and in a decoding stage, respectively reading the weight and the first key value cache by utilizing the PIM chip, and writing the second key value cache of the Token generated by the large model into the DRAM chip. According to the method, the processing engine in the PIM chip is utilized, data only need to be read from the FLASH and the DRAM which are closest in physical distance, delay is reduced, model weight data and key value cache data do not need to be read through a bus route, data carrying is reduced, and power consumption is reduced.

A cloud-based configurator system and method for the automated design and engineering of electrical switchboards is disclosed. The system includes a web-based interface and a cloud-hosted configurator engine that accesses a database of pre-engineered copper bus components and current inventory data. The configurator automatically generates, evaluates, and selects optimal copper bus routing solutions between designated points using combinations and permutations of existing parts. The system prioritizes in-stock components to reduce manufacturing lead times and optimize cost-efficiency, while eliminating the need to design custom components for each new order. Additional features include dynamic pricing based on spot market data, CRM integration for pre-populating configuration fields, mobile compatibility, generation of AutoCAD-compatible technical drawings, and multi-vendor switchboard variant generation. An administrative dashboard supports configuration management, user analytics, inventory updates, and approval workflows, enabling faster manufacturing throughput, improved customer responsiveness, and increased profitability.

The invention discloses a real-time task arbitration method of a heterogeneous OS cluster and related equipment, and relates to the technical field of computers, the method comprises the following steps: collecting a resource request signal, task priority data, a global timestamp and a resource identifier of a multi-core processor through a hardware interface; performing standardized mapping on task priority data, and dynamically calculating an effective priority based on waiting time; aiming at concurrent resource request signals of resources of the same resource identifier, arranging the resource request signals in a descending order according to effective priorities through a hardware sorting network, and performing timestamp defeat on the highest priority group by adopting a global timestamp; sending a resource authorization signal to the winning core and configuring a bus route; and dynamically adjusting a priority weighting parameter according to the historical arbitration data. According to the method, various data are collected through a hardware interface, then calculation is effective, then the global timestamp is adopted to carry out decision arbitration, and a priority hardware-assisted cross-OS real-time arbitration scheme can be realized.

The invention relates to the technical field of flight simulation communication, and discloses a flight simulation hierarchical communication system and method based on cloud native dual-bus scheduling, and a communication architecture based on hierarchical decoupling, and the system comprises a component application module, a bus intelligent scheduling module, a data distribution module and a transmission adaptation module which are connected in sequence. The component application module is used for docking various flight simulation components; the bus intelligent scheduling module comprises a control bus unit and a data bus unit which are physically isolated from each other, and an intelligent scheduling unit which is in communication connection with the control bus unit and the data bus unit, and is used for realizing type identification of transmission data, branch and bus routing and dynamic scheduling of transmission resources based on a flight simulation scene; and the data distribution module comprises a cloud resource adaptation engine and a subscription relationship management unit, and is used for docking a cloud platform resource pool and realizing heterogeneous deployment resource matching and communication channel subscription management of various flight simulation components.

The application discloses a bus wiring method based on GoldenBit and Hanan grid updating, which comprises the following steps: firstly, generating the GoldenBit topology path of each component, and then wiring other pin feet; then, before each wiring, performing dynamic Hanan grid updating; for each edge of the Hanan grid, according to whether it is a segment and a line extended from a component, the edge is divided into different priorities; finally, according to the different priorities, adjusting the wiring path, finding the shortest path while ensuring that the topology path is as same as the last path as possible, so as to complete the bus wiring.

A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an update register control output, and a shift output; a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output; an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and address circuitry having address inputs coupled to the address outputs, and having an enable output.

This application provides a bus routing method for integrated circuits, an electronic device, and a computer-readable storage medium, relating to the field of integrated circuits, to solve the problem of time-consuming and labor-intensive bus routing in integrated circuits. The method includes: displaying a first interface, the first interface including a first control for indicating project creation. In response to a first operation on the first control, a project is created, and a second interface is displayed; the created project includes pins to be connected in the integrated circuit and the connection relationships of the pins to be connected; the second interface includes information on multiple groups and a second control; the multiple groups are obtained by automatically pre-grouping multiple connections, and the multiple connections are obtained according to the connection relationships of the pins to be connected. In response to a second operation on the second control, the result of automatic routing of the connections included in each group is output. This method is used to improve the efficiency of bus routing.

The invention discloses an event bus dynamic routing distribution method, device and equipment and a storage medium, relates to the field of computers, is applied to a terminal carrying a dynamic routing distribution system, and comprises the following steps: obtaining a target event, and determining a multi-dimensional feature corresponding to the target event by using a target feature extraction model; based on the multi-dimensional features of the target event and the real-time state of the dynamic routing distribution system, determining a routing path corresponding to the target event by using a target decision model, and obtaining a theoretical quantification result corresponding to each routing path by using a target reward function; the routing path is a known routing path corresponding to the event type of the target event; and determining a target routing path from all routing paths corresponding to the target event based on the theoretical quantification result, and distributing the target event to a target event queue corresponding to the target routing path based on the target routing path. According to the method and the device, the event bus route distribution mode is improved, and the route distribution requirement in a high-concurrency and complex dynamic scene is met.

The invention relates to the technical field of electric energy management, in particular to a wind-solar-storage integrated edge data center power supply system, which comprises an energy power acquisition module, an overlapping degree calculation module, an energy storage scheduling module, a bus routing module and a thermoelectric control module. According to the method, the instantaneous power of wind energy and light energy is collected in real time and subjected to dynamic normalization processing, a filtering algorithm is combined, noise is accurately eliminated, a high-adaptation data center power sequence is generated, and fine identification of load fluctuation and dynamic adjustment of the power supply guarantee rate are achieved through vector analysis and window marking. When the guarantee rate is reduced, an energy storage response compensation scheme is intelligently optimized, instant self-matching supplement of electric energy supply is achieved, an energy supply structure is adjusted according to real-time parameters of a line, the voltage change amplitude is accurately monitored to actively trigger thermal management measures, and the linkage effect of energy consumption control and electric power fluctuation reduction is formed. The matching performance of the power efficiency and the load working condition is remarkably improved, and the risk hidden danger caused by instability of renewable energy sources is reduced.

The invention discloses a chip capable of saving bus routing, which comprises a master hardcore module and at least two slave hardcore modules, the master hardcore module comprises a chip bus master device, each slave hardcore module comprises an instruction conversion unit, a data synchronization unit and a register, the chip bus master device generates a JTAG instruction, and the JTAG instruction is transmitted to the slave hardcore module. A clock signal, a TMS signal and a TDI signal contained in a JTAG instruction are sent to each instruction conversion unit through a TCK signal line, a TMS signal line and a TDI signal line respectively, and the instruction conversion unit converts the TDI signal into an APB operation instruction and sends the APB operation instruction to the data synchronization unit; under the driving of the clock signal, based on the TMS signal and the TDI signal, obtaining output data, and sending the output data to a chip bus master device through a TDO signal line; the data synchronization unit carries out time sequence synchronization on the APB operation instruction and sends the APB operation instruction to the register for configuration; and the chip bus master device selects the output data and outputs the output data to the APB. According to the invention, low power consumption can be realized.

The embodiment of the invention provides a cross-bus route detection method and device, electronic equipment and a storage medium. The cross-bus route detection method comprises the steps of obtaining a source end and a destination end of each route link in a vehicle; determining a routing link of which the corresponding source end and target end do not belong to the same bus as a target link; simulating a source end of the target link to generate a test signal, and sending the test signal through a bus to which the source end of the target link belongs; and judging whether the to-be-detected signal received by the destination end of the target link is the same as the test signal, if so, judging that the routing detection result of the target link is normal, and if not, judging that the routing detection result of the target link is routing failure. According to the method, targeted detection is carried out on the cross-bus routing link, the limitation that the prior art is limited to a single bus detection scene is broken through, data interaction faults among different bus systems can be found in time, cooperative failure and functional abnormality of the systems of the vehicle are avoided, and potential safety hazards are reduced.

The invention discloses an anti-collision control circuit and method for a wireless communication signal, and relates to the technical field of wireless communication, the anti-collision control circuit comprises an RISC-V core processor, a bus routing circuit, an APB bus, a digital baseband circuit, an RIB bus, a read-only memory and a random access memory, the bus routing circuit is respectively connected with the RISC-V core processor, the APB bus and the RIB bus, the RIB bus is respectively connected with the read-only memory and the random access memory, and the APB bus is connected with the digital baseband circuit; the RISC-V core processor comprises an instruction fetching circuit, a decoding circuit and an execution circuit; the digital baseband circuit comprises a sending link circuit, a receiving link circuit, a multiplexing circuit, a baseband controller and an anti-collision algorithm hardware acceleration circuit. According to the method, the calculation delay is remarkably reduced while the algorithm is ensured to be flexible and configurable, and the identification efficiency and the system throughput performance in a multi-label dense scene are improved.