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Laser radar receiver front-end readout integrated circuit pixel unit layout structure

A technology for reading integrated circuits and laser radars, which is applied in the fields of instruments, electrical digital data processing, and special data processing applications, etc., and can solve the problems of increased difficulty in layout design of pixel units of readout processing circuits, RC parasitic effects, and uneven processing Array circuit power supply wiring and other issues to achieve the effect of improving consistency and anti-interference ability, reasonable layout, and optimized area

Pending Publication Date: 2021-01-05
SUZHOU R&D CENT OF NO 214 RES INST OF CHINA NORTH IND GRP
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AI Technical Summary

Problems solved by technology

As the scale of the array continues to expand, RC parasitic effects and uneven processing will adversely affect the wiring of the clock and power supply of the array circuit, making it more difficult to design the pixel unit layout of the matching readout processing circuit

Method used

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  • Laser radar receiver front-end readout integrated circuit pixel unit layout structure

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Embodiment Construction

[0022] The present invention will be further described below in conjunction with the accompanying drawings. The following examples are only used to illustrate the technical solution of the present invention more clearly, but not to limit the protection scope of the present invention.

[0023] see figure 1 As shown, it is a schematic diagram of the layout structure of the pixel unit of the front-end readout integrated circuit of the lidar receiver implemented in this embodiment. In this embodiment, the layout area of ​​the pixel unit is 100 μm*100 μm, the array size is 64*64, and a 0.18 μm, 6-layer metal process is adopted. The layout structure includes a first layout area 10 , a second layout area 20 , a third layout area 30 , a fourth layout area 40 and a fifth layout area 50 . Wherein, the first layout area 10 is connected to the second layout area 20 , the second layout area 20 is connected to the third layout area 30 , and the third layout area 30 is connected to the fou...

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Abstract

The invention discloses a laser radar receiver front-end readout integrated circuit pixel unit layout structure, which is characterized in that a first layout area is connected with a second layout area, the second layout area is connected with a third layout area, and the third layout area is connected with a fourth layout area and a fifth layout area; the first layout area is an In column interconnection layout area; the second layout area is a trans-impedance amplifier layout area; the third layout area is a time sequence control circuit layout area; the fourth layout area is a row selection bus routing layout area; and the fifth layout area is an input row driving layout area. According to the invention, layout design of all pixel units can be completed in a limited area, the area is optimized, and the chip cost is reduced; the column interconnection area, the analog circuit module and the digital circuit module are effectively isolated, adverse effects on wiring of a clock and a power supply of an array circuit due to an RC parasitic effect and uneven technological processing are considered, and the consistency and the anti-interference capability of a pixel unit circuit are improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, relates to a chip layout structure, in particular to a laser radar receiver front-end readout integrated circuit pixel unit layout structure. Background technique [0002] In aerospace, shipbuilding, rail transit, high-end manufacturing and other fields, lidar is widely used in target tracking and positioning. Lidar is mainly composed of a laser transmitter, receiver, signal processing module and display. The receiver is one of the core components of Lidar. The receiver system structure consists of a photodiode and a front-end readout circuit pixel unit array. As the scale of the array continues to expand, RC parasitic effects and uneven processing will adversely affect the wiring of the clock and power supply of the array circuit, making it more difficult to design the pixel unit layout of the matching readout processing circuit. Contents of the invention [0003] The techni...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/392G06F30/398
CPCG06F30/392G06F30/398Y02A90/10
Inventor 吕江萍
Owner SUZHOU R&D CENT OF NO 214 RES INST OF CHINA NORTH IND GRP
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