Formation method of semiconductor structure

Abstract

A method for forming a semiconductor structure comprises the following steps: providing a substrate which comprises a target layer for forming a target pattern; forming a core layer extending along a first direction on the substrate, wherein a direction perpendicular to the first direction is a second direction; forming a side wall on the side wall of the core layer, wherein the core layer and the side wall located on the side wall of the core layer form a graphic structure layer; forming a sacrificial layer crossing the graphic structure layer in the second direction on the substrate, wherein the sacrificial layer at least covers part of the top and part of the side wall of the graphic structure layer; forming a flat layer on the substrate exposed by the sacrificial layer and the graphic structure layer; the sacrificial layer is removed, first grooves are formed in the flat layer, and the first grooves are located in the two sides of the pattern structure layer; the core layer is removed, so that a second groove is defined by the side walls; and etching the target layer below the first groove and the second groove by taking the flat layer and the side wall as masks to form a target pattern. The embodiment of the invention is beneficial to further compressing the pitch between the target patterns.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure. Background technique [0002] With the rapid growth of the semiconductor integrated circuit (Integrated circuit, IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's Law, making integrated circuits smaller in size, higher in circuit precision, and development in the direction of higher complexity. [0003] During the development of integrated circuits, usually as the functional density (that is, the number of interconnection structures per chip) gradually increases, the geometric size (that is, the minimum component size that can be produced using process steps) also gradually decreases. Correspondingly increases the difficulty and complexity of integrated circuit manufacturing. [0004] At present, how to improve the matching degree between t...

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Problems solved by technology

[0003] During the development of integrated circuits, usually as the functional density (that is, the number of interconnection structures per chip) gradually increases, the geometric size (that is, the minimum component size that can be produced using process steps) also gradually decreases. Correspondingly increases the difficulty and complexity of integrated circuit manufacturing

[0004] At present, in the case of shrinking technology nodes, how to improve the matching degree between the pattern formed on the wafer and the target pattern has become a challenge

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