Wafer-level reconfigurable Chiplet integrated structure

Abstract

The invention belongs to the technical field of semiconductor packaging, and particularly relates to a wafer-level reconfigurable Chiplet integrated structure which comprises a tube shell, a first substrate, an RDL, a second substrate, a cavity, a functional Chiplet, a reconfigurable topology network, through holes, a third substrate, a Chiplet communication network, a fourth substrate, micro bumps and solder balls. The integrated structure sequentially comprises a third substrate, a fourth substrate, a Chiplet communication network, a second substrate, a cavity, a functional Chiplet, a reconfigurable topology network, a through hole, a micro bump, a first substrate, an RDL and a solder ball from top to bottom. The tube shell is arranged on the upper side of the fourth substrate, and the side end of the tube shell is fixedly connected with the first substrate. A wafer-level reconfigurable Chiplet integrated structure is adopted, a design normal form, which is high in cost, low in yield and high in design difficulty, of a traditional SoC-based integration technology can be converted into a wafer-level-based Chiplet integration direction which is larger in scale, higher in efficiency and lower in design difficulty, the reuse rate of the wafer-level Chiplet is further increased through the reconfigurable technology, and the manufacturing cost is greatly reduced.

Description

technical field [0001] The present application belongs to the technical field of semiconductor packaging, and in particular relates to a wafer-level reconfigurable Chiplet integration structure. Background technique [0002] Traditional SoCs have the problems of process incompatibility and design difficulty. With the further increase of process node scaling and integration scale, system function verification time increases, leakage power consumption continues to rise, and chip yield, reconfigurability, and reliability The scalability continues to decline, unable to meet the low-cost, high-performance system requirements of diversified application scenarios. This results in low integration efficiency, scalability, and poor yield of electronic systems, which restricts the development of high-performance, low-cost microsystems. [0003] The authorized patent number is "CN110473792B", and the patent title is "A Reconstruction Method for Integrated Circuit Wafer Level Packaging"...

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a wafer-level reconfigurable Chiplet integrated structure to solve the problem that the integrated structure does not have reconfigurability in the prior art, resulting in the solidification of the function of the integrated structure.

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