Method of fabricating nanowire-based structure and capacitor array assembly including same
A technology of capacitor components and manufacturing methods, applied in the field of integration, capable of solving problems such as separation
Pending Publication Date: 2022-04-29
MURATA MFG CO LTD +1
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Problems solved by technology
[0010] In the case of an analog mixed-signal SOC, there are strict restrictions on power domain isolation: i.e., GND and VSS must be separated for both the analog and digital domains
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Embodiment Construction
[0047] Embodiments of the present invention address the deficiencies of the prior art by providing nanowire structures capable of forming multi-capacitor assemblies in which individual capacitors are isolated from each other. A multi-capacitor assembly can be created by forming a stack of insulator layers and electrode layers over the nanowire group. Formation of the capacitive stack above the nanowires providing a highly open geometry makes the proposed structure well suited for the deposition of electrode layers and insulator layers of capacitive stacks. The preferred nanowire structure provides additional advantages in terms of higher stress tolerance and thus makes it possible to achieve improved ESR / ESL (equivalent series inductance) and EPC (equivalent capacitance density).
[0048] More specifically, the first embodiment of the present invention provides figure 1 Multi-capacitor assembly 1 is shown.
[0049] Such as figure 1 As shown, the example multi-capacitor asse...
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Abstract
A nanowire structure (5) is fabricated by forming conductive material islands (30a, 30b) on a substrate (10-20) and forming a conductive sacrificial layer (40) in a space (35) between the conductive islands. The conductive islands (30a, 30b) include an anode etch barrier layer (30). An anodically oxidizable layer (50) is formed over the conductive islands and sacrificial layers and anodized to form a porous template (60). The nanowires (70) are formed in a region (A) of the porous template that overlaps the conductive islands (30a, 30b). Removal of the porous template and the sacrificial layer leaves a nanowire structure (5) comprising an isolated set of nanowires connected to respective conductive islands (30a, 30b) acting as current collectors. Respective stacks of conductive layers and insulator layers are formed over different nanowire sets to form respective capacitors that are electrically isolated from each other. Accordingly, a monolithic assembly including an array of isolation capacitors formed over the nanowire may be formed.
Description
technical field [0001] The present invention relates to the field of integration, and more particularly to methods of fabricating integrated nanowire-based structures and multi-capacitor assemblies incorporating such nanowire-based structures, and to capacitor array assemblies fabricated using such methods. Background technique [0002] Technologies have been developed to integrate passive components in silicon. For example, the PICS technology developed by Murata Integrated Passive Solutions (Murata Integrated Passive Solutions) enables the integration of high-density capacitive components into silicon substrates. Depending on the technology, dozens or even hundreds of passive components can be efficiently integrated into a silicon die. [0003] For example, in P. Banerjee et al. entitled "Nanotubular metal-insulator-metal capacitor arrays for energy storage (nanotube metal-insulator-metal capacitor arrays for energy storage)" (May 2009 in Nature Nanotechnology (nature nan...
Claims
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IPC IPC(8): H01G4/33H01G4/38C25D1/00C25D1/04C25D11/02C25D11/04H01L49/02H10N97/00
CPCH01G4/33H01G4/38C25D1/006C25D1/04C25D11/022C25D11/045H01L28/90H01G4/012H01G4/306Y02E60/13H01L21/02603H01L23/5223H01L29/0676
Inventor 朱利安·埃尔萨巴希弗雷德里克·瓦龙久伊·帕拉特
Owner MURATA MFG CO LTD