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Wafer-level fan-out packaging structure and preparation method thereof

A packaging structure, wafer-level technology, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc. The effect of slice time

Pending Publication Date: 2022-05-03
甬矽半导体(宁波)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the past, the overall tape-out time of wafer-level fan-out packaging was as long as one month, which took a long time, and it was a test for the chip packaging foundry.

Method used

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  • Wafer-level fan-out packaging structure and preparation method thereof
  • Wafer-level fan-out packaging structure and preparation method thereof
  • Wafer-level fan-out packaging structure and preparation method thereof

Examples

Experimental program
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no. 1 example

[0062] see figure 1 and Figure 10 , this embodiment provides a method for preparing a wafer-level fan-out packaging structure, which is used to prepare a wafer-level fan-out packaging structure 100, and the wafer-level fan-out packaging structure 100 is a fully encapsulated structure. The preparation method of the wafer-level fan-out packaging structure provided in the example can greatly reduce the difficulty of the process by using the mature flip-chip process, and can realize the comprehensive encapsulation of the functional chip 131 to improve the reliability of the package, and has the advantages of short overall packaging time and Advantages such as low cost shorten the process flow time and effectively improve the tape-out time of wafer-level fan-out packaging.

[0063] The preparation method of the wafer-level fan-out packaging structure provided in this embodiment includes the following steps:

[0064] S1: Prepare a functional chip 131 with a first conductive pilla...

no. 2 example

[0093] This embodiment provides a method for preparing a wafer-level fan-out packaging structure. Its basic steps, principle and technical effects are the same as those of the first embodiment. For a brief description, what is not mentioned in this embodiment can be Refer to the corresponding content in the first embodiment.

[0094] The preparation method provided in this embodiment comprises the following steps:

[0095] S1: Prepare a functional chip 131 with a first conductive pillar 133 processed on one side.

[0096] see in conjunction Figure 11 , process and cut copper cylinders on wafers of functional chips 131 of different sizes. Specifically, firstly at least two functional wafers 130 are provided, each functional wafer 130 has a plurality of functional areas for forming a functional chip 131, and then first conductive pillars of different sizes are formed on the functional wafer 130 133 , and finally dicing the functional wafer 130 to form functional chips 131 of...

no. 3 example

[0110] This embodiment provides a method for preparing a wafer-level fan-out packaging structure. The basic steps, principles and technical effects are the same as those of the first or second embodiment. For brief description, this embodiment does not mention Where it is concerned, reference may be made to the corresponding content in the first embodiment or the second embodiment.

[0111] The preparation method provided in this embodiment comprises the following steps:

[0112] S1: Prepare a functional chip 131 with a first conductive pillar 133 processed on one side.

[0113] see in conjunction Figure 11 , process and cut copper cylinders on wafers of functional chips 131 of different sizes. Specifically, firstly at least two functional wafers 130 are provided, each functional wafer 130 has a plurality of functional areas for forming a functional chip 131, and then first conductive pillars of different sizes are formed on the functional wafer 130 133 , and finally dicin...

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Abstract

The embodiment of the invention provides a wafer-level fan-out packaging structure and a preparation method thereof, and relates to the technical field of chip packaging, the method can prepare a functional chip and a substrate wafer at the same time, after the functional chip and the substrate wafer are prepared, the functional chip is mounted on a chip mounting area in an inverted manner, then a plastic package body is arranged on the substrate wafer, and the plastic package body is used for packaging the functional chip and the substrate wafer. And then wiring is completed on the plastic package body to form a wafer wiring layer, and finally cutting is carried out after ball mounting is carried out on the wafer wiring layer. Compared with the prior art, the manufacturing method has the advantages that the substrate wafer and the functional chip can be manufactured at the same time, the functional chip is directly attached to the substrate wafer to complete chip manufacturing, and compared with a conventional method of sequentially forming a hierarchical structure, the manufacturing method can greatly reduce the process difficulty and improve the production efficiency. The wafer-level fan-out packaging method has the advantages that the packaging reliability is improved, the overall packaging time is short, the cost is low and the like, the technological process time is shortened, and the tape-out time of wafer-level fan-out packaging is effectively improved.

Description

technical field [0001] The invention relates to the technical field of chip packaging, in particular to a wafer-level fan-out packaging structure and a preparation method thereof. Background technique [0002] With the rapid development of the semiconductor industry, wafer-level fan-out packaging structures are widely used in the semiconductor industry. As chips become smaller and the number of signal contacts increases, traditional packaging can no longer meet the demand for high contact counts. Wafer-level fan-out packaging technology (FOWLP) is a supplement to wafer-level chip size packaging technology. The chip signal contact port is led out by reconfiguring the wafer, and solder balls or bump terminals are formed on the reconstructed plastic package. Array, within a certain range, can replace the traditional wire bond and ball array (WBBGA) package or flip chip ball array (FCBGA) package (<500 signal contacts) package structure, especially suitable for the booming p...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/56H01L21/48H01L23/31H01L23/498
CPCH01L21/561H01L21/4846H01L23/3107H01L23/49838H01L23/49811
Inventor 钟磊李利张超何正鸿
Owner 甬矽半导体(宁波)有限公司
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