Super-large-scale heterogeneous FPGA (Field Programmable Gate Array) layout method considering clock constraint

A super-large-scale, layout-based technology, applied in instrumentation, computing, electrical and digital data processing, etc., can solve problems such as poor FPGA layout results, and achieve the effect of improving FPGA performance, reducing wiring line length, and improving layout quality.

Pending Publication Date: 2022-05-13
SOUTHEAST UNIV
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Problems solved by technology

[0007] The purpose of the present invention is to provide a kind of very large-scale heterogeneous FPGA lay

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  • Super-large-scale heterogeneous FPGA (Field Programmable Gate Array) layout method considering clock constraint
  • Super-large-scale heterogeneous FPGA (Field Programmable Gate Array) layout method considering clock constraint
  • Super-large-scale heterogeneous FPGA (Field Programmable Gate Array) layout method considering clock constraint

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Embodiment Construction

[0051] The technical solution of the invention will be described in detail below in conjunction with the accompanying drawings.

[0052] The present invention provides a super-large-scale heterogeneous FPGA layout method considering clock constraints. The method first performs connection-aware and type-balanced clustering based on a given netlist and architecture, and then uses hybrid penalty augmentation considering heterogeneity and clock-awareness. The wide Lagrangian method and Adam-based optimizer are used for multi-level module placement, followed by IP legalization and multi-stage packaging, and finally CLB-level global layout and CLB legalization. Such as figure 1 As shown, the method includes the following steps:

[0053] 101. According to a given FPGA netlist and architecture, a hierarchical structure is constructed by using a connection-aware and type-balanced clustering method;

[0054] 102. In each level, a hybrid penalized augmented Lagrangian method is used to...

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Abstract

The invention discloses a super-large-scale heterogeneous FPGA (Field Programmable Gate Array) layout method considering clock constraint, which comprises the following steps of: (1) constructing a hierarchical structure by adopting a clustering method of connection perception and type balance according to a given netlist and architecture; (2) in each level, modeling the heterogeneous and clock-aware layout into a series of unconstrained optimization sub-problems by adopting a mixed penalty augmented Lagrange method, and executing Adam to solve each sub-problem; (3) executing IP block legalization based on matched clock sensing; (4) obtaining an HCLB-level netlist by adopting a multi-stage packaging strategy; (5) executing clock-driven global layout to improve the layout quality; and (6) finally, a CLB legalization method based on history is adopted to ensure layout legality. According to the method, on the premise of meeting clock constraints, a high-quality layout result can be quickly obtained, the wiring length is effectively reduced, and the requirement of the current super-large-scale FPGA layout stage can be met.

Description

technical field [0001] The invention relates to a super-large-scale heterogeneous FPGA layout method considering clock constraints, and belongs to the technical field of FPGA physical design automation. Background technique [0002] A Field Programmable Gate Array (FPGA) is a logic device that can be reprogrammed to implement user customization. As an integrated circuit, FPGA has the advantages of low risk and high design flexibility. Compared with ASICs, FPGAs can quickly enter the market at a lower cost and are suitable for high-end control applications. FPGA is one of the fastest growing fields in the semiconductor industry and has become a research hotspot in academia and industry. [0003] In order to meet emerging circuit design requirements, FPGA has achieved innovative evolution in architecture. In order to improve the integration level of the circuit, the logic block of modern FPGA presents large-scale and heterogeneous characteristics. The CLB architecture has ...

Claims

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Application Information

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IPC IPC(8): G06F30/347
CPCG06F30/347
Inventor 朱自然梅扬杰
Owner SOUTHEAST UNIV
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