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Hybrid logic multiply-accumulate circuit based on memristor

A hybrid logic and memristor technology, applied in the field of hybrid logic multiply-accumulate circuits, can solve problems such as hardware architecture performance limitations, and achieve the effect of reducing area, realizing the integration of storage and computing, and reducing power consumption

Pending Publication Date: 2022-05-24
UNIV OF SCI & TECH OF CHINA
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  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

However, as Moore's Law reaches its limit and computing and storage are separated, the performance of these hardware architectures will eventually be limited

Method used

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  • Hybrid logic multiply-accumulate circuit based on memristor
  • Hybrid logic multiply-accumulate circuit based on memristor
  • Hybrid logic multiply-accumulate circuit based on memristor

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Embodiment Construction

[0021] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

[0022] figure 1 A memristor-based AND logic circuit is shown, a x is the input, b i (i=0, 1, 2, 3) store data for the memristor, c i (i=0, 1, 2, 3) is the output, V open is the gate voltage, R g is the ground resistance, R on g off , R off and R on are the high and low resistance values ​​of the memristor, respectively. When V open is high, the row of transistors is gated, if the input a x =0, the output is 0, if a x =1, when the memristor is i...

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Abstract

The invention discloses a hybrid logic multiply-accumulate circuit based on memristors. The circuit comprises a data buffer, a memristor array, a shifter, a summator and a register. Input data is input through the data buffer, the data buffer is connected to the memristor array, and cached data is input into the memristor array; the output of the memristor array is connected to the shifter, the shifter is connected with a clock signal and a plurality of summators, the result after shifting of the shifter is input to the summators, the result is added to the original data of the register through the summators, and the result is stored in the register again. According to the invention, through combination of the memristor and the CMOS circuit, data storage is realized, and logic operation is completed; by combining the circuit, the area can be reduced, the power consumption can be reduced, and storage and calculation integration can be realized.

Description

technical field [0001] The present invention relates to the field of integrated memory-computing architecture, in particular to a memristor-based hybrid logic multiply-accumulate circuit. Background technique [0002] In the era of big data, as the scale of processing data becomes larger and larger, the computing and storage separation architecture of the von Neumann structure can no longer meet the increasing performance requirements. The storage-computing integrated architecture can effectively solve the storage wall and power consumption wall problems faced by the Fung structure. [0003] In recent years, in order to break through the performance bottleneck of the Feng-style structure, GPU, FGPA and various ASICs came into being. However, with Moore's Law reaching its limits and the separation of compute and storage, the performance of these hardware architectures will eventually be limited. Therefore, the memory-computing integrated architecture based on the new compon...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/544
CPCG06F7/5446Y02D10/00
Inventor 孙文浩吴启樵陈松
Owner UNIV OF SCI & TECH OF CHINA
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