Parallel form verification method and device, computer equipment and medium
A formal verification and layered verification technology, applied in computer-aided design, computing, instruments, etc., can solve problems such as inability to manage and control multiple parallel execution tasks well, so as to save overall simulation time and improve verification efficiency Effect
Pending Publication Date: 2022-07-01
SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
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Problems solved by technology
The current formal verification platform can only submit and execute one task at a time, so it can only use sequential execution
In addition, although the existing formal verification can well manage and control the simulation process of a single task and the analysis of the simulation results, it cannot manage and control multiple tasks executed in parallel.
Method used
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[0048] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention will be further described in detail below with reference to the specific embodiments and the accompanying drawings.
[0049] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities with the same name but not the same or non-identical parameters. It can be seen that "first" and "second" It is only for the convenience of expression and should not be construed as a limitation to the embodiments of the present invention, and subsequent embodiments will not describe them one by one.
[0050] First of all, it is stated that the abbreviations and keys that appear in the following examples belong to the definition:
[0051] Tool Command Language (TCL for short): Tool Command Language;
[0052] Hierarchical Verificati...
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The invention relates to the technical field of integrated circuits, in particular to a parallel form verification method and device, computer equipment and a medium. The method comprises the steps that a formal verification task corresponding to each verification demand is defined based on a plurality of verification demands, and each formal verification task is provided with an entry file of a verification environment; adding the name of the defined formal verification task into a hierarchical verification plan file; in response to the received verification request, reading the names of the defined formal verification tasks from the hierarchical verification plan file, and copying the corresponding formal verification task to a working directory of a verification platform according to the name of each formal verification task; and searching and running an entry file of each form verification task in the working directory to start a plurality of form verification tasks. According to the scheme, multiple form verification tasks are processed at the same time, the total simulation time consumed by form verification can be greatly saved, and the verification efficiency is remarkably improved.
Description
technical field [0001] The present invention relates to the technical field of integrated circuits, and in particular, to a parallel formal verification method, device, computer equipment and medium. Background technique [0002] With the increasing integration and complexity of chips, the difficulty of functional verification is also increasing rapidly. How to define a complete verification space to fully cover all possible application scenarios of the chip is a challenge that verification engineers are facing. Formal verification is a method based on strict mathematical algorithms and models, which extracts the property description of the circuit according to the design specification, exhaustively and traverses all possible states of the circuit during the operation of the system under reasonable constraints, and automatically performs mathematical analysis and proof. new verification method. Formal verification has become more and more widely used in the industry due to...
Claims
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IPC IPC(8): G06F30/3323G06F30/12
CPCG06F30/3323G06F30/12
Inventor 崔盼宋强丁明阳
Owner SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD