Synchronous rectification driving circuit with low transmission delay
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[0021] In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.
[0022]The present invention proposes a synchronous rectification drive circuit with low transmission delay. The system block diagram is as follows: Figure 4 As shown, it mainly includes a falling edge detection circuit, a pull-up current control circuit, a comparator CP1, an inverter N1, a single-pulse trigger circuit 1, a single-pulse trigger circuit 2, an RS flip-flop RS1, and a pull-up transistor Q. 1 and drop tube Q 2 . v in the figure D and v S Respectively, the synchronous rectifier S R The drain and source voltages of , and have v DSR =v D -v S , v IU_...
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