Dynamic random access memory and manufacturing method thereof

Abstract

The invention provides a dynamic random access memory and a manufacturing method thereof. The dynamic random access memory comprises a buried word line, a bit line, a bit line contact structure, a capacitor contact structure and an air gap structure. The embedded word line is formed in the substrate and extends along a first direction. The bit lines are formed on the substrate and extend along a second direction. The bit line contact structure is formed below the bit line. The capacitor contact structure is adjacent to the bit line and surrounded by the air gap structure. The air gap structure comprises a first air gap and a second air gap which are located on the first side and the second side of the capacitor contact structure respectively. The first air gap exposes the shallow trench isolation structure in the substrate. The second air gap exposes the top surface of the substrate. The parasitic capacitance between the bit line and the capacitor contact structure can be obviously reduced. The air gap structure extending into the shallow trench isolation structure is beneficial to reducing the resistance value of the bit line contact structure and the capacitance contact structure, and can further reduce the parasitic capacitance.

Description

technical field [0001] The present invention relates to a memory device, and more particularly, to a dynamic random access memory and a method of manufacturing the same. Background technique [0002] In dynamic random access memory (DRAM), parasitic capacitances are generated between bit lines and adjacent capacitive contact structures. If the parasitic capacitance is too large, the bit corresponding to the bit line will be difficult to distinguish between 0 and 1, and the writing speed will be reduced. As a result, the performance and yield of the product will be reduced. As memory devices are miniaturized, the distance between bit lines and adjacent capacitive contact structures decreases. Therefore, the above-mentioned parasitic capacitance problems will become more serious. [0003] The parasitic capacitance can be reduced by reducing the height (or thickness) of the bit line. However, the resistance value of the bit line increases. As a result, the operation of the...

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Problems solved by technology

In this way, the chip area will increase, which is not conducive to the miniaturization of memory devices.

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