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Semiconductor device

A semiconductor and conduction technology, applied in the field of three-dimensional flash memory devices, can solve the problems of reduced read and write speeds

Pending Publication Date: 2022-08-02
FU TAI HUA IND SHENZHEN +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The main purpose of the present invention is to provide a semiconductor device, aiming to solve the problem of lower reading and writing speed in the prior art

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  • Semiconductor device
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Embodiment Construction

[0033] In order to make those skilled in the art better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only Embodiments are part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0034] The terms "first", "second" and "third" in the description of the present invention and the above drawings are used to distinguish different objects, rather than to describe a specific order. Furthermore, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system,...

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Abstract

A semiconductor device includes a plurality of memory cells. Each storage unit comprises a laminated structure, a barrier layer, a floating gate layer, a tunnel dielectric layer and a channel layer. The stacked structure includes at least one control layer, at least one erase layer, and at least one dielectric layer. The barrier layer and the control layer are arranged in a coplanar manner, and the floating gate layer is accommodated in the barrier layer and is insulated from the control layer through the barrier layer. The tunnel dielectric layer covers one side of the barrier layer and one side of the floating gate layer. The channel layer is located on one side of the tunnel dielectric layer. The erasing layer is used for applying a predetermined voltage when data read-out and write-in operations are executed, so that the series resistance value of the channel layer is reduced, and rapid conduction of the semiconductor device is facilitated.

Description

technical field [0001] The present invention relates to a semiconductor device, in particular to a three-dimensional flash memory device. Background technique [0002] In the current semiconductor industry, three-dimensional (3D) flash memory can keep stored information for a long time without powering on, and has the advantages of high integration, fast storage speed, and easy erasing and rewriting. With the development of technology, it has become a trend that the size of 3D flash memory gradually becomes smaller. The cross-sectional area of ​​the channel layer in the 3D flash memory structure becomes smaller, and it is not easy to reduce the series resistance in the vertical direction by means of ion implantation, etc., thereby reducing the writing speed of the 3D flash memory when performing data writing operations. SUMMARY OF THE INVENTION [0003] The main purpose of the present invention is to provide a semiconductor device, which aims to solve the problem of reduc...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11517H01L27/11521H01L27/11551H10B41/00H10B41/20H10B41/27H10B41/30
CPCH10B41/00H10B41/20H10B41/30H10B41/27H01L29/42328
Inventor 陈中怡
Owner FU TAI HUA IND SHENZHEN