Structure and read-write method of double-bit non-volatile memory unit

Abstract

A storage unit contains two pile-grids structure, a mixed area in between and two source / leakage areas outside with the style of the same as the mixed. When writing, the channel under the two pile-grids will be open simultaneously to select the floating grid to be written by the director of the channel and impose fetch bias, transfer bias of the first and second control grid about the first flooding grid to decide if to write the data according to the conduction of the two source / leakage grid areas, among which, the fetch bias is bigger than the initial voltage of the route on erasure state, smaller than the initial voltage on writing state which is smaller than the transfer bias.

Description

technical field [0001] The present invention relates to a structure of a semiconductor device (Semiconductor Device) and an operation method thereof, and in particular to a double-bit non-volatile storage unit (Double-Bit N non- V olatile M The structure of emory(NVM)Unit) and its reading and writing methods. Background technique [0002] Non-volatile memory (NVM) is a permanent storage medium with fast access speed, small size, power saving and vibration resistance, so it is widely used. The most important type of non-volatile memory is flash memory (Flash Memory), which is characterized by erasing data block by block (Block by Block), which can save the time required for erasing operations. [0003] For the structure of traditional non-volatile memory cells (Memory Cell), please refer to figure 1 . Such as figure 1 As shown, there is a stacked gate structure 110 on the substrate 100 , and there are source / drain regions 120 in the substrate 100 on both sides thereof. ...

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Problems solved by technology

therefore. There will be an alignment problem between the floating gate 214 and the control gate 218 / transfer gate 218a, so that the width of the transfer gate 218a and the relationship between the control gate 218 / transfer gate 218a and the floating The overlapping area of ​​the gate 214 is prone to errors, making the electrical properties of each memory cell inconsistent, and increasing the difficulty of operating the memory

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