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Method for producing integrated circuit

A technology of integrated circuit and circuit structure, which is applied in the direction of circuit, semiconductor/solid-state device manufacturing, electrical components, etc., and can solve problems such as high scrap rate

Inactive Publication Date: 2004-12-22
GIESECKE & DEVRIENT GMBH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The disadvantage of the above method is that each metallization structure is connected to a circuit structure and high alignment accuracy is required when bonding these structures, otherwise a high reject rate must be tolerated

Method used

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  • Method for producing integrated circuit
  • Method for producing integrated circuit
  • Method for producing integrated circuit

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0040] Figure 1a A starting substrate with a processed silicon chip 1 , ie provided with a circuit structure, is shown. A first metallization structure 2 has been applied on the silicon chip, comprising wiring elements 3 and in Figure 1a The case has three layers. One of these metallization layers, preferably the topmost layer, can be designed as a drilling protection layer. This layer makes it possible to recognize whether an attempt has been made to remove the metallization layer in order to read the contents of the circuit structure, for example a memory.

[0041] Figure 1b The wafer assembly is shown after the next method step, in which plated through holes 4 have been etched into the circuit structure 1 , penetrating through the first metallization structure 2 .

[0042]then, Figure 1c The assembly is shown after the plated-through holes 4 are insulated with an insulating layer 6 and after metallization with a conductive material 5 (or connection line) to create ...

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PUM

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Abstract

The invention relates to a method for producing an integrated circuit according to which first a first substrate is provided with a circuit structure and a superimposed metallization structure consisting of one or more layers and having plated through holes extending as far as the wafer's rear side. The plated through holes are insulated in relation to the circuit structure and a planarization layer is arranged on top of the metallization structure. The first wafer obtained in this manner is bonded to a handling wafer and the first substrate is thinned from the rear so that the plated through holes are open and the metallized connections exposed. A problem arising in the manufacture of integrated circuits is their wiring, which is becoming increasingly complex as the width of structures decreases and functionalities increase and is thus difficult to produce. The aim of the invention is to provide a method which makes it possible to wire even complex integrated circuits at acceptable cost and low reject rates. To this end a second metallization layer is created on the rear side of the chip and connected to the first metallization structure and / or circuit structure by means of the plated through holes.

Description

technical field [0001] The invention relates to a method of manufacturing integrated circuits in two-sided processing, circuits manufactured by this method, and modules and portable cards having circuits thus manufactured. Background technique [0002] A particular problem in conventional integrated circuit production is that of wiring (or wiring), which is becoming more complex as feature widths shrink and functionality increases. This means that the metallization is carried out on multiple layers in the wiring of the chip, or that the number of layers increases with increasing chip complexity. This creates the difficulty that a limited number of metallization layers can only be formed layer by layer. [0003] Vertical integrated circuits are disclosed in the prior art. Vertical system integration provides a method by which one chip or wafer is thinned and bonded to another chip or wafer. A method for producing three-dimensional integrated circuits is known, for example,...

Claims

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Application Information

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IPC IPC(8): H01L21/768H01L21/822H01L27/00H01L27/04
CPCH01L21/8221H01L21/76898H01L2924/0002H01L2924/00
Inventor 托马斯·格拉斯尔
Owner GIESECKE & DEVRIENT GMBH