Embedded internal storage test platform device and testing method

Abstract

The present invention relates to test platform set and its test method. It applies to system integration single chip with embedded internal storage. The set consists of a tested IC socket in which the system integration single chip is inserted, a reference IC socket in which can independent internal storage device is inserted, and a test control circuit connected to both the tested IC socket and the reference IC socket electrically. The test control circuit writes in comparable data to the tested embedded internal storage and the independent internal storage integrated circuits, then reads them out. When the read out data are not identical, it will stop writing in and reading out and send the wrong data to the computer to be recorded and analysed.

Description

Technical field [0001] The invention relates to a test platform device and a test method thereof, in particular to a test platform device and a test method applied to a system integration single chip with an embedded memory. Background technique [0002] Today's semiconductor integrated circuits mainly include a logic control circuit part and a memory part, and their functions and manufacturing methods are different, so they are generally fabricated on different chips. In industries with fine division of labor and their respective strengths, different professional teams usually produce the finished products before assembling them. However, with consideration of various factors such as cost, reliability, and execution speed, embedded chips, or so-called System On Chips (SOC) have become a trend. See figure 1 , A functional block diagram of a system integration single chip 1, which mainly has a logic control circuit 11 and an embedded memory 12, and the logic control circuit 11 an...

AI Technical Summary

Problems solved by technology

However, when using common integrated circuit tester (IC tester) to perform the above-mentioned round-trip process of testing and modifying the design, it is time-consuming to compile test patterns separately.

Moreover, the test algorithms provided by the designers of static random access memory are not able to provide a comprehensive and rigorous test for embedded memory, so that many possible failure patterns cannot be detected and recorded Down, so that its testing and error checking procedures will take too long and delay the delivery time, resulting in heavy losses

[0005] The reason for this is that the test program executed on common integrated circuit tester (IC tester) and the functions that the hardware can provide are not test software and hardware developed for the purpose of debugging, so there is no It is the main purpose of the present invention to efficiently complete the error detection (debug) program required by the system integration single chip, and how to develop an appropriate and efficient test platform and error detection method, and then improve the defects of the above-mentioned common technical means

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