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Vertical MOS transistor

A transistor and polysilicon technology, applied in the field of vertical MOS transistors, can solve problems such as threshold voltage fluctuations

Inactive Publication Date: 2005-04-13
SII SEMICONDUCTOR CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, since N - Diffusion fluctuations in type high concentration region 21 and P - The implantation depth of the type diffusion region 20 fluctuates, the peak concentration also tends to fluctuate, and the threshold voltage thus tends to fluctuate as well.

Method used

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Embodiment Construction

[0045] Embodiments of the present invention will be described below with reference to the drawings.

[0046] figure 1 is the N of the embodiment of the present invention - A cross-sectional view of the main part of a trench vertical MOS transistor. N - The epitaxial layer 2 is formed on the N + On the substrate 1, the trench structure gate electrode 5 is covered by N - The epitaxial layer is covered by gate oxide film 4, P - The body region surrounds gate oxide film 4 . N + The source region 7 is in contact with the side surface of the gate oxide film 4, and the N + source region 7 adjacent to the P + Diffusion region 9 is formed on the surface of N epitaxial layer 2 . Form P around the gate oxide film 4 - Type body region 17, in N + source region 7 and P - N - source region 6. P + Diffusion region 8 is formed in P + Below the body contact zone 9. And the insulating film 10, and P + body contact region 9 and N + A metal electrode connected to the source reg...

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PUM

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Abstract

Provided is a vertical MOS transistor in which high-frequency characteristics are improved, low-voltage operation is achieved, and stable characteristics with small fluctuations are obtained. After the trench gate is oxidized, oblique ion implantation is used to form the body region on the sidewall. After the gate electrode is formed, oblique ion implantation is used to form a low-concentration source region, thereby suppressing the capacitance between the gate and the source and the capacitance between the gate and the drain. . When the above body region formation method is adopted, the impurity distribution between the drain and source of the channel region is also made uniform. In addition, since the channel length is determined by the etching equipment, a stable channel length can be obtained by using the same equipment for trench etching and gate electrode etching.

Description

technical field [0001] The present invention relates to a vertical MOS transistor having a trench structure. Background technique [0002] As discrete power transistors replacing bipolar transistors, MOS transistors have been adopted in recent years, and their driving power has been improved and their costs have been reduced. Since this power MOS transistor has a structure that allows current to flow in a direction perpendicular to the substrate, it is called a vertical MOS transistor, and is often used in large current situations, such as in applications requiring low power loss and low on-resistance situation, etc., as an external driver of the IC to control the current of the ampere level. In particular, using image 3 Compared with the traditional planar vertical DMOS transistor, the vertical trench DMOS transistor with the trench structure shown has the advantage that the cell pitch is small, but it does not increase the parasitic resistance. Mainstream structure of o...

Claims

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Application Information

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IPC IPC(8): H01L21/265H01L21/336H01L29/08H01L29/10H01L29/78
CPCH01L21/26586H01L29/086H01L29/0869H01L29/1095H01L29/7813
Inventor 原田博文
Owner SII SEMICONDUCTOR CORP