Correction circuit, delay circuit and annular oscillator circuit

A technology for calibrating circuits and circuits, applied in electrical pulse generator circuits, pulse manipulation delays, and logic circuits to generate pulses, etc., can solve problems such as inability to use, and achieve the effects of reducing power consumption and stabilizing delay time.

Inactive Publication Date: 2006-04-26
SHARP KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, when the time period until this voltage is obtained from the standby-release state is too long, the correction circuitry 230 and the delay circuit including the correction circuitry 230 cannot actually be used for such a long time.

Method used

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  • Correction circuit, delay circuit and annular oscillator circuit
  • Correction circuit, delay circuit and annular oscillator circuit
  • Correction circuit, delay circuit and annular oscillator circuit

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0101] The present invention will be described below by way of example with reference to the accompanying drawings.

[0102] figure 1 An example delay circuit 40 according to the invention is shown. previously discussed about Figure 8 with 16 The same elements have the same reference numerals, and their detailed descriptions will be omitted below.

[0103] The delay circuit 40 includes a first correction circuit 10 and a second correction circuit 20, instead of Figure 8 A first correction circuit 210 and a second correction circuit 220 in the delay circuit 200 are shown. The gate of the p-channel transistor 204a included in the inverter circuit 205a receives the voltage (control signal) generated in the first correction circuit 10 . The gate of the n-channel transistor 204b included in the inverter circuit 205b receives the voltage (control signal) generated in the second correction circuit 20 . Except for these points, the delay circuit 40 has the same circuit config...

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PUM

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Abstract

A correction circuit for generating a control signal to correct a characteristic change of a first transistor, comprising: a control signal adjustment section including a constant voltage reducing element for determining one of a maximum voltage and a minimum voltage of the control signal, and a second transistor for determining the characteristics of the control signal, the gate of the second transistor receiving a prescribed voltage; and a resistor portion including two types of resistor elements having temperature-dependent characteristics of resistance values ​​different from each other, the resistor The elements are connected in series. The constant voltage reducing element, the second transistor, and the resistor portion are connected in series between the power supply terminal and the ground terminal. The control signal is output from a connection point between the control signal adjustment section and the resistor section. The constant voltage reducing element includes a transistor. The drain of the transistor included in the voltage lowering element is connected to the source of the second transistor, and the drain of the second transistor is connected to one end of the resistor portion.

Description

technical field [0001] The present invention relates to a correction circuit for use in a correction circuit for generating a control signal that corrects a change in characteristics caused by production conditions or physical conditions such as changes in power supply and temperature conditions in transistors included in semiconductor integrated circuits; And the delay circuit and the ring oscillator circuit in this correction circuit. In particular, the present invention relates to a correction circuit, a delay circuit and a ring oscillator circuit which can be preferably used to generate a reference clock generation circuit (timing generation circuit) in, for example, an internal subsynchronous semiconductor memory device. Background technique [0002] In CMOS semiconductor integrated circuits, some delay circuits used as timing generating circuits or the like use CMOS transistors. A delay circuit using a CMOS transistor utilizes the signal transmission delay characteris...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K5/13H03K19/003H03K3/011H03K3/03H03K3/354H03K5/00
CPCH03K3/011H03K3/0315H03K5/133H03K2005/00026H03K2005/00039H03K2005/0013H03K2005/00143H03K2005/00208
Inventor 森川佳直
Owner SHARP KK
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