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Data transmission method and data transmission system

A technology of data transmission and transmission operation, which is applied in the direction of electrical digital data processing, instruments, etc., to achieve the effect of improving the efficiency of use

Inactive Publication Date: 2007-01-24
SHANGHAI MAGIMA DIGITAL INFORMATION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This data transmission method can send a large amount of data continuously at one time, but there are still certain defects, because the burst data transmission requires that the data must be on consecutive addresses.

Method used

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  • Data transmission method and data transmission system

Examples

Experimental program
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Effect test

example 1

[0082] Figure 5 Shown is a timing diagram of each signal in a non-interrupted data transfer.

[0083] Wherein, the MAdd signal indicates the address of data transmission; the MData signal indicates the transmitted data; the MCmd signal is a forward transmission command, which is low read and high write in this embodiment. From Figure 5 It can be seen that this is a complete flow burst, which contains three segmented bursts.

[0084] The MLast signal before the end of the first segment burst is a SAME signal, that is, the target address of data transmission is no longer continuous, but it is still in the same slave device. Therefore, in the second segment burst, the MDstnum signal is the same as the first segment burst, both are slave device A (its code is 0), and the Madd signal is 0x20, which is the same as the first segment burst target address Discontinuous. The third segmented burst is a segmented burst of CREQ level, and the MLast signal before the end of the second...

example 2

[0087] Figure 6 Shown is a timing diagram of each signal in an interrupted data transfer. For the convenience of explanation, in the figure, MReq1, MLast1, MAdd1, MData1, MDstnum1, MCmd1 represent the request signal of the data transmission operation performed by the master device A; Request signal for data transfer operations. The ALast signal is a signal sent by the arbiter 107 after responding to MLast1 and MLast2.

[0088] Figure 6 A stream burst transfer operation of master device A in the Figure 5 The operation of the master device is exactly the same, but because the master device A is interrupted by the higher-level bus request of other master devices during this stream burst transmission operation, the timing of the stream burst of the master device A is also generated accordingly some changes. and Figure 5 The master device in the same, Figure 6The bus request of master A in is a complete stream burst, including four segmented bursts. but Figure 6 The ...

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Abstract

It is a kind of data transmission method and system. The data transmission operation goes through between master equipment and slave equipment by bus. It comprises: arbitrating the bus usage request from master equipment; the master equipment gets the authority through arbitration and performs the flow burst data transmission operation, at the same time sends the bus control signal to bus. If the bus control signal is CONT signal, it continues the segment burst data transmission operation of current flow burst data transmission operation; if the bus control signal is SAME signal or DIFF signal, it detects whether there is some bus request with higher priority from other master equipment. When detecting that other master equipment issues new bus request with higher priority, it arbitrates this request and next segment burst request of flow burst data transmission operation of current master equipment. The master equipment that gets the authority transmits data preferentially. If the bus control signal is LAST signal, it returns to initial operation.

Description

technical field [0001] The invention relates to a data transmission method and a data transmission system. In particular, it relates to a method and system for quickly and efficiently transmitting data between a master device and a slave device using a bus in an architecture with multiple master devices. Background technique [0002] In order to realize fast and real-time signal processing, computer systems, especially multi-processor systems, are often equipped with multiple fast functional processing units to facilitate corresponding control and data processing at the same time. The processing units in the system may include various devices such as central processing unit (CPU), digital signal processor (DSP) and memory. Especially in a system on a chip, it is often necessary to integrate a large number of devices on the same chip at the same time. In consideration of various aspects such as area and cost, resource sharing between processing units is often implemented in...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/38
Inventor 周振亚孙民梁
Owner SHANGHAI MAGIMA DIGITAL INFORMATION
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