Strong dielectric memory
A ferroelectric and storage device technology, applied in information storage, static memory, digital memory information, etc., can solve the problems of large memory area and inability to increase capacity, and achieve the effect of reducing power consumption
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no. 1 Embodiment approach
[0035] (Explanation of its structure)
[0036] Fig. 1 is a block diagram of a FeRAM of a ferroelectric memory device according to a first embodiment of the present invention, and Fig. 2 is a perspective view schematically showing its memory array. As shown in FIG. 2 , the memory cell array 10 has a ferroelectric film 12 , a plurality of word lines 14 arranged on one side of the ferroelectric film 12 , and a plurality of bit lines 16 arranged on the other side of the ferroelectric film 12 .
[0037] With the above structure, ferroelectric memory cells 18 are formed at respective intersections (intersection type) of the plurality of word lines 14 and the plurality of bit lines 16 as shown in FIG. 1 . According to this configuration, the memory as shown in FIG. 2 is called a cross-point type FeRAM or a passive type FeRAM. In this way, the memory shown in Figure 2 has an active memory with a 1T / 1C unit configured with a transistor and a capacitor (ferroelectric) on each unit, or ...
no. 2 Embodiment approach
[0076] Fig. 8 shows a second embodiment of the present invention in which a pre-drive operation is performed before the short-circuit operation. This pre-drive action is, for example, an action after the read action (write "0" action) as shown in Figure 4. Before the short-circuit action as shown in Figure 5, the word line 14 and the bit line 16 connected to the selection unit 18a are Pre-driving is performed at any potential between 0 and Vs by the word line driver 20 and the bit line driver 22 .
[0077] If the potential 2Vs / 3 or Vs / 3 supplied from the power supply circuit 24 is also used as the pre-drive potential, there is no need to prepare a new pre-drive potential.
[0078] The word lines 14 and bit lines 16 connected to the selected cell 18a are also extremely smaller than the total number of word lines 14 and bit lines 16 connected to many unselected cells 18b. Therefore, the load capacity for connecting the word line 14 and the bit line 16 connected to the selection...
no. 3 Embodiment approach
[0082] Fig. 10 is a block diagram of a third embodiment of the present invention. The first difference from FIG. 1 is that the common short-circuit line 32 is grounded. The second difference is that instead of supplying the common gate control line 36 of the short circuit switch 34 with the short circuit sequence signal generated during the “short circuit operation” shown in FIG. 7 and FIG. Through the timing generator circuit 40.
[0083] An example of the power-on timing generating circuit 40 shown in FIG. 10 is shown in FIG. 11 , and its operation timing chart is shown in FIG. 12 . PEQ1 output from the power-on timing generating circuit 40, as shown in FIG. The threshold voltage Vth of the transistor 34 is higher than or equal to that of the transistor 34 . In this way, even after the power is turned on, the short-circuit operation in the short-circuit circuit 30 is performed. This result makes it possible to connect all word lines 14 and bit lines 16 of FIG. Potential...
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