Method for manufacturing semiconductor integrated circuit device

Abstract

The invention provides a production method for semiconductor integrated circuit device for improving the breakdown voltage of transistors in the dielectric separated complementary bipolar transistor of an NPN transistor and a longitudinal PNP transistor. In the production method for semiconductor integrated circuit device, when forming the collector area and collector extraction area of the semiconductor integrated circuit device, by laminating four epitaxial layers, the buried layer of the collector area and the buried layer of the collector extraction area are simultaneously formed for each epitaxial layer. Then, the respective buried layers are diffused, linked and etched to a V groove die. Thus, the collector area and collector extraction area made into thick films are simultaneously formed and breakdown voltage is improved.

Description

technical field [0001] The present invention relates to a semiconductor integrated circuit device and a manufacturing method thereof which realize a high withstand voltage transistor by forming a collector region thicker in a dielectric isolation type complementary bipolar transistor. Background technique [0002] In recent years, transistors used in audio amplifiers, display drivers, etc. have been required to achieve higher withstand voltage and higher integration. In order to achieve high integration and high speed of high withstand voltage integrated circuits, it is best to use dielectric isolation technology to prevent the formation of parasitic transistors or the increase in chip size caused by the formation of element isolation. [0003] exist Figure 13 A cross-sectional view of an exemplary prior art semiconductor integrated circuit device is shown in (for example, Japanese Patent Application Laid-Open No. 11-354535). Also, refer to Figure 14 ~ Figure 20 , shown ...

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