Semiconductor memory device and memory modulus and system adopting same

Abstract

A semiconductor memory device includes a clock buffer which receives an external clock signal and generates a first internal clock signal having a frequency lower than that of the external clock signal and a second internal clock signal having a frequency which is the same as that of the external clock signal. An address buffer, command signal buffer and / or register receive respective input signals at a timing of the first internal clock signal. On the other hand, a data buffer inputs / outputs data at a timing of the second internal clock signal.

Description

technical field [0001] The invention relates to a memory device, a memory module and a system, in particular to a semiconductor memory device generating an internal clock signal and a memory module and a system using the semiconductor memory device. Background technique [0002] The growing need for computer systems capable of processing large amounts of data at high speeds has led to the continued development of efficient microprocessors or central processing units (CPUs), which tend to run at higher and higher system clock frequencies. One of the requirements for the use of a higher system clock frequency is an increase in the data capacity and transfer speed of the data memory interfaced with the CPU. In other words, the memory must be configured to run synchronously with the higher frequency system clock signal. [0003] figure 1 is a diagram of the memory controller 110 and the memory module 120 of the CPU system board 100 . The storage controller 110 transmits a clo...

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Problems solved by technology

Likewise, the operating characteristics of register 108 may limit the effective operating speed of the memory to less than the system clock speed

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