Design method of built-in parallel two-dimensional discrete wavelet conversion VLSI structure

Abstract

The design method of built-in parallel two-dimensional discrete wavelet conversion VLSI structure includes: to adopt shift addition technology to change multiplication operation in filter into shift register and adder operation; to adopt sharer expression technology to reduce the number of shift register and adder for realizing the filter; to adopt filter merging technology to merge the common terms of both high-pass and low-pass filters and to realize parallel both high-pass and low-pass operation in one compact hardware structure; and to adopt filter combination merging technology to merge two 2-DDWT filters into one and to raise the hardware utilization. The present invention is one high-efficiency 2-DDWT scheme with very high hardware utilization and other advantages.

Description

[0001] 1. Field [0002] The invention belongs to the technical field of VLSI design. Specifically, it involves designing a parallel and efficient hardware structure design method of 2-D discrete wavelet transform (2-D DWT) in JPEG2000 hardware implementation. 2. Background technology [0003] In many practical systems, such as digital cameras, videophones, camcorders, and handheld computers, it is necessary to use chips to implement compression systems in consideration of speed and area requirements. Among the existing 2-D DWT chip structures, most of the structures have exactly the same structural design for the two stages of fast discrete wavelet transform (row filtering and column filtering). Although this reduces the control complexity, it also reduces Hardware utilization increases chip cost. In addition, in the current chip structure, the operation results of the high-pass filter and the low-pass filter are output in turn in each stage. This structure not only reduces...

AI Technical Summary

Problems solved by technology

Among the existing 2-D DWT chip structures, most of the structures have exactly the same structural design for the two stages of fast discrete wavelet transform (row filtering and column filtering). Although this reduces the control complexity, it also reduces hardware utilization, increasing chip cost

In addition, in the current chip structure, the operation results of the high-pass filter and low-pass filter are output in turn in each stage. This structure not only reduces the hardware utilization rate, but also limits the speed at which the chip processes data.

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