Crystal covered package substrate

Abstract

A crystal covered packaging substrate is composed of the multilayer patternized wire layer in at least one insulation layer and at least one conductive plug of which the wire layer is overlapped to each other in sequence, the insulation layer is configurated in between the two adjacent wire layers and the conductive plug is running through the insulation layer to connect the wire layers electrically. There are several lug pads at top layer of the wire layers and there are several welding ball pads at bottom layer of the wire layers. In addition, there are multicircles of lug pad rings formed by lug pads at the top face of the crystal covered packaging substrate and multicircules of welding ball pad rings formed by welding ball pads corresponded to the lug pad ring at the bottom face of which the internal-external relative positions of lug pad rings.

Description

technical field [0001] The present invention relates to a flip-chip substrate, and in particular to a flip-chip substrate capable of reducing planar inductance effects and synchronous switching noise (Synchronous Switching Noise, SSN). Background technique [0002] Flip Chip technology (Flip Chip, FC) is a packaging technology often used in Chip Scale Package (CSP). Die pads are arranged on the active surface of the chip, and bumps are formed on each pad, and then the bumps on the chip are connected to the contacts of the carrier (carrier) correspondingly. contact), the so-called bump pad. Since the flip-chip bonding technology has the advantages of reducing the packaging area and shortening the signal transmission path, the flip-chip bonding technology has been widely used in the field of chip packaging. [0003] Please refer to figure 1 , which is a cross-sectional view of a known flip-chip structure. The flip-chip substrate 20 is mainly composed of multi-layer pattern...

AI Technical Summary

Problems solved by technology

However, the signal solder ball pads 136a, the power solder ball pads 136b and the ground solder ball pads 136c of the known flip-chip package substrate 130 are all irregularly distributed on the bottom surface 134 of the flip-chip package substrate 130, which does not correspond to meets the Figure 2A The internal and external distribution of the signal pad 106a, the power pad 106b and the ground pad 106c of the chip 100 will increase the winding length between the pad 106 and the corresponding solder pad 136, resulting in a longer current path. Produces a large planar inductance value, and the corresponding inductance value varies greatly

Images