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Semiconductor storage and method for testing same

A storage device and semiconductor technology, applied in the direction of information storage, static memory, digital memory information, etc., can solve problems such as insufficient, and achieve the effect of easy operation and simple circuit structure

Inactive Publication Date: 2003-03-12
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0028] Therefore, of course, it can be considered that the control that can only be simply set to the wait state like ordinary SRAM is not enough.
Therefore, it is necessary to provide in advance a wait mode unique to quasi-SRAM, which is not available in conventional SRAM.

Method used

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  • Semiconductor storage and method for testing same
  • Semiconductor storage and method for testing same
  • Semiconductor storage and method for testing same

Examples

Experimental program
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Effect test

no. 1 approach

[0088] figure 1 is a block diagram showing the configuration of the semiconductor memory device according to the present embodiment. In this figure, an address Address is an access address provided from outside the semiconductor memory device. Corresponding to a memory cell array arranged in rows and columns, the address Address includes a row address and a column address. The address buffer 1 buffers the address Address and outputs it.

[0089] The latch 2 takes the address provided by the address buffer 1 as it is while the latch control signal LC is at "L (low)" potential (that is, between the fall of the latch control signal LC and the next rise of the latch control signal LC). output while internal L_ADD. In addition, when the latch control signal LC rises, the latch 2 takes out the address provided by the address buffer 1, holds the address while the latch control signal LC is at H (high) potential, and uses the held address as an internal The address L_ADD is output...

no. 2 approach

[0203] The present embodiment realizes the same function as that of the page mode employed in a general DRAM or the like. Figure 12 is a block diagram showing the configuration of the semiconductor memory device according to the present embodiment, and figure 1 The same constituent elements and signal names are denoted by the same reference numerals. In the present embodiment, by dividing the address Address described in the first embodiment into the upper bit address UAddress and the lower bit address PageAddress (page address), only changing the address page address PageAddress for the same bits of the upper address UAddress Group input and output can be realized.

[0204] For example, since the address PageAddress is 2 bits wide in this embodiment, by making the address PageAddress change within the range of "00"B to "11"B (its value B refers to binary count), segmental access is possible 4 consecutive addresses. The width of the address PageAddress is not limited to 2 ...

no. 3 approach

[0213]In each of the above-mentioned embodiments, regardless of whether the access request provided by the outside is a read request or a write request, the change of the address Address (including the case where the chip select signal / CS is valid) is used as a trigger, and the read is performed after the update is performed. output or write operation.

[0214] On the other hand, in this embodiment, when there is a read request, the read operation is performed first, and then the update is performed. In this way, it is possible to increase the reading speed (short access time) compared to the above-described embodiments. When there is a write request, similar to the above embodiments, the update is performed first, and then the write operation is performed.

[0215] Figure 14 It is a block diagram showing the configuration of the semiconductor memory device of this embodiment. Since the configuration of the semiconductor memory device shown in this figure is the same as t...

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Abstract

The invention provides a semiconductor memory device incorporating memory cells the same as for DRAM and which operates under SRAM specification, where the chip size is small and power consumption and cost are low, and for which access delay or memory cell data destruction due to skew incorporated in an address does not arise. An ATD circuit (3) generates a one shot pulse for an address transition detection signal (ATD) from transition of an externally supplied address (Address). At this time, by generating the one shot pulse for each bit of the address and then combining these, then even in the case where the address contains a skew, the one shot pulse is only generated once. At first, refresh is performed during the generation period of the one shot pulse, using a refresh address (R_ADD) generated by a refresh control circuit (4). Then, on receipt of a fall in the one shot pulse, a latch control signal (LC) is generated, the address is latched by the latch (2) and the memory cell array (6) accessed.

Description

technical field [0001] The present invention relates to a semiconductor memory device whose memory cell array is composed of the same memory cells as DRAM (Dynamic Random Access Memory), and which is similar to SRAM (Static RAM) when viewed from the outside of the semiconductor memory device. ) same format action. In particular, the present invention relates to a semiconductor memory device which is compatible with an SRAM capable of asynchronously supplying a write enable signal for determining a write timing to a memory cell with respect to a write address. . Background technique [0002] The most representative semiconductor memory devices capable of random access are SRAM and DRAM. Compared with DRAM, SRAM is generally faster, and as long as the power is supplied and the address is input, the change of the address can be captured, the internal sequence circuit is activated, and the read and write operations are performed. In this way, compared with DRAM, SRAM can oper...

Claims

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Application Information

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IPC IPC(8): G11C8/18G11C11/406G11C29/12
CPCG11C8/18G11C29/12G11C11/406G11C11/40615G11C11/401
Inventor 高桥弘行稻叶秀雄草刈隆
Owner RENESAS ELECTRONICS CORP