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Memory cell structure integrated on semiconductor

A storage unit, semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, transistors, etc., can solve the problem of lack of scalability

Inactive Publication Date: 2003-07-30
STMICROELECTRONICS SRL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] However, the structure described in the above-mentioned literature is an extended structure, so, from the perspective of the plane, it lacks scalability

Method used

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  • Memory cell structure integrated on semiconductor
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Embodiment Construction

[0022] specific implementation plan

[0023] The process steps and structures described below are not intended to be a complete flow for fabricating integrated circuits. In practice, the present invention can be implemented with integrated circuit technology currently used in the industry, and only those common conventional process steps necessary to make the present invention understandable are described here.

[0024] The cross-sectional views showing the integrated circuit in its manufacture are not drawn to scale, but they are indeed drawn to emphasize the main features of the invention.

[0025] Refer to these figures, especially figure 1 For example, a polysilicon substrate (such as P-type) 2 is schematically represented by reference numeral 1, has an upper surface 3, and includes two doped regions (such as n-type doping) 4, which are arranged near the surface 3 and separated from each other . In this embodiment, these regions 4 are the source / drain regions of the tra...

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Abstract

This invention relates to a memory cell which comprises a capacitor having a first electrode and a second electrode separated by a dielectric layer. Such dielectric layer comprises a layer of a semi-insulating material which is fully enveloped by an insulating material and in which an electric charge is permanently present or trapped therein. Such electric charge accumulated close to the first or to the second electrode, depending on the electric field between the electrodes, thereby defining different logic levels.

Description

technical field [0001] The present invention relates to the storage unit structure integrated on the semiconductor, both can be used for the volatile memory such as DRAM (Dynamic Random Access Memory), also can be used for EPROM, EEPROM (Electrically Erasable Programmable Read-Only Memory) or flash EEPROM such of non-volatile memory. More particularly, the invention relates to memory cells of this type comprising a capacitor having a first electrode and a second electrode separated by a dielectric layer. The invention also includes a method of storing information in a memory cell comprising a capacitor having a first electrode and a second electrode separated by a dielectric layer. Background technique [0002] As is known, the fabrication of semiconductor integrated electronic memory devices involves both volatile and non-volatile memories. A structure of non-volatile memory cells such as cells of the EPROM, EEPROM and flash EEPROM type, and one of the volatile memory cel...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8247H01L29/788H01L29/792H10B12/00
CPCH01L29/7882H01L29/792
Inventor 萨尔瓦托·隆巴尔多科西莫·杰拉尔迪伊索蒂亚娜·克鲁皮马西莫·梅拉诺特
Owner STMICROELECTRONICS SRL