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Secure programmable logic device

A technology for programming logic, multi-chip components, applied in logic circuits, logic circuits using basic logic circuit components, logic circuits using specific components, etc., can solve problems such as increasing the complexity and cost of memory chips and target programmable devices

Inactive Publication Date: 2003-09-24
ATMEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, while encrypting bits is relatively easy to implement, encrypting the data stream will add significant complexity and cost to the memory chip and target programmable device

Method used

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Examples

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Embodiment Construction

[0010] exist figure 2 Among them, a multi-chip assembly (module) with external leads 29 has mounted therein a SRAM-based programmable logic chip 21 and a configuration memory chip 23, which form a single package. The programmable logic chip 21 may be a field programmable gate array (FPGA), a programmable logic device (PLD) configurable in the system, or other logic that needs to be loaded with configuration when powered on. External leads 29 are connected to the chips 21 and 23, and internal data connections 27 connect the configuration memory chip 23 to the logic chip 21 in such a way that the configuration can be loaded into the logic chip 21 when power is applied. The multichip assembly can form a system-level integrated circuit device that combines logic, memory, and a microcontroller in a single package.

[0011] The configuration memory 23 has two changes, the first being the addition of encryption bits 24. When the encryption bit is set, it is not possible to read bac...

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PUM

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Abstract

A programmable logic chip (21) and configuration memory chip (23) are both mounted in a multi-chip module (25) to form a single package. The configuration memory has an encryption bit (24). When it is in the first state, the readback of the configuration data in the memory chip can be programmed through the external leads (29) of the package. When the encryption bit is in the second state, Only the erase command can communicate with the memory chip through the external lead. The internal data transmission link (27) provided between the memory chip and the programmable logic chip can only be activated when the encryption bit is in the second state and the memory chip is in readback mode, thereby allowing configuration data to be loaded at power-on into the logic chip.

Description

technical field [0001] The present invention relates to SRAM-based programmable logic integrated circuits, such as Field Programmable Arrays (FPGAs), in which the configuration code forming the programmed function of the logic circuit is loaded into the logic circuit at power-on from a configuration memory or a microcontroller of. In particular, the invention relates to a scheme for protecting the contents of the configuration store from being copied. Background technique [0002] As the density of programmable logic integrated circuits becomes denser, the price becomes cheaper, and the speed becomes faster, this programmable logic integrated circuit is more and more widely used in the design of mass-produced products, instead of Gate arrays or standard cell ASICs used in the past. This transition to programmable logic circuits opens up opportunities for design theft that would be less of an opportunity for ASICs under the same conditions. There is a particular "concern" ...

Claims

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Application Information

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IPC IPC(8): G06F21/12G06F12/14G06F21/10G06F21/14H03K19/173H03K19/177H04L9/10
CPCG06F12/1433G06F21/606G06F21/74G06F21/76G06F21/79G06F2221/2105G06F2221/2143H03K19/17704H03K19/17768H03K19/177
Inventor M·T·梅森N·D·昆纳利H·H·郭
Owner ATMEL CORP
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