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Clock signal transmission circuit

A clock signal and transmission circuit technology, applied in the direction of circuit, logic circuit, signal generation/distribution, etc., can solve the problems of low driving ability, excessive wiring capacitance, power consumption, etc.

Inactive Publication Date: 2004-06-02
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] However, in order to reduce power consumption, the driving capability of the buffer that operates by a low-frequency clock signal is suppressed to be low.
Therefore, when this buffer supplies a low-frequency clock signal to the transmission wiring, excessive power is consumed due to excessive wiring capacitance.

Method used

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  • Clock signal transmission circuit
  • Clock signal transmission circuit
  • Clock signal transmission circuit

Examples

Experimental program
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Effect test

Embodiment 1

[0029] figure 1 It is a structural circuit diagram of Embodiment 1 of the present invention. The clock generator 10a selectively outputs a first clock signal having a first frequency and a second clock signal having a second frequency. However, the second frequency is set higher than the first frequency. Either output of the first clock signal or the second clock signal is supplied to the clock output wiring 49 as an output clock.

[0030] The clock signal input to the clock output wiring 49 is output to the NAND gate 53 at the same time as the write permission signal WE. The output of the NAND gate 53 is input to the clock input terminal of the logic element 20 to control the writing operation of the logic element 20 .

[0031] The clock signal transmission circuit includes clock transmission lines 41 and 42 . Although the first clock signal is transmitted to the clock transmission line 42 by the function of the selector 81 a described later, the second clock signal is no...

Embodiment 2

[0070] Fig. 5 is the structural circuit diagram of embodiment 2 of the present invention, figure 1 In the structure shown in , a structure for distributing the first clock signal and the second clock signal is added.

[0071] The first clock transmission wiring group 201 has figure 1 The shown clock transmission wiring 42 , the relay inverter 62 that relays the first clock signal therebetween, the clock transmission wiring 41 , the relay inverter 61 that relays the second clock signal therebetween, and the control wiring 91 . The first clock transmission line group 201 is connected to the clock transmission networks 21 and 22 . In Fig. 5, for the sake of simplification, details of the mesh are omitted, and only the outermost shape (here, ring shape) is shown.

[0072] The clock transmission networks 22 and 21 each have a function of distributing the first clock signal and the second clock signal to a plurality of units. The clock transmission net 21 is wider than the wiring...

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PUM

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Abstract

To transmit a clock signal while optimizing an operation speed and a power consumption in accordance with the frequency of a given clock signal. A clock generator 10a outputs either one of a first clock signal or a second clock signal. The frequency of the second clock signal is higher than that of the first clock signal. A selector 81a is controlled by a control signal CNTL1 and provides a clock transmission wiring 42 with the first clock signal when the same is outputted from the clock generator 10a while providing the clock transmission wiring 41 with the second clock signal when the same is outputted from the clock generator 10a. The width of the clock transmission wiring 41 is wider than that of the clock transmission wiring 42. A selector 82a is controlled by the control signal CNTL1 and connects either one of the clock transmission wirings 41, 42 to the outside of the circuit.

Description

technical field [0001] The present invention relates to techniques for transmitting clock signals. Background technique [0002] An integrated circuit with multiple operating frequency modes is designed to operate even at a set maximum operating frequency. In an integrated circuit, the higher the frequency of the clock signal on which this operation is based, the higher the high-speed operation is required, and the power consumption tends to increase. Therefore, although this integrated circuit has a structure corresponding to high-speed operation, when the frequency of the received clock signal is low, large unnecessary power is consumed. [0003] Therefore, there is a proposal of a technique of transmitting a clock signal using a plurality of buffers that selectively operate according to the frequency of a given clock signal. For example, Patent Document 1 exemplifies related art. [0004] [Patent Document 1] [0005] Japanese Patent Application Publication No. 10-2092...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/06H01L21/82H01L21/822H01L27/02H01L27/04H03K5/00H03K5/15
CPCG06F1/06H03K5/15H01L27/0207
Inventor 伊藤仁一
Owner RENESAS ELECTRONICS CORP