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Processor and compiler for creating program for the processor

A processor and program execution technology, applied in the field of branch instructions, which can solve problems such as reducing real-time performance

Inactive Publication Date: 2004-09-01
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0014] However, in an IC card system using a processor as described above, the condition determination program must be executed while performing a transfer from the user program 302 to the supervisor program 301, and thus the real-time performance is reduced

Method used

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  • Processor and compiler for creating program for the processor
  • Processor and compiler for creating program for the processor
  • Processor and compiler for creating program for the processor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0037] will refer to the attached figure 1 One embodiment of the processor 400 of the present invention is described.

[0038] figure 1 A block diagram of an IC card system using the processor 400 of this embodiment is shown.

[0039] Such as figure 1 As shown, the IC card system includes the following: CPU 401; instruction ROM 402; RAM403; flash memory 404; external I / F 405; antenna coil 406; address bus 407a; data bus 407d; interrupt control circuit 408; invalid branch detection circuit 409 Execution area judgment circuit 410; Execution work mode judgment circuit 411; Branch destination judgment circuit 412; Branch destination work mode judgment circuit 413;

[0040]The CPU 401 includes an instruction retrieval unit 4011 , an instruction decoding unit 4012 , an instruction execution unit 4013 , a program counter 4014 , and a memory access control circuit 4015 .

[0041] CPU 401 reads instructions from instruction ROM 402 or flash memory 404 and then executes the instr...

Embodiment 2

[0058] The following is a description of an IC card system using the processor 400 of Embodiment 2 of the present invention.

[0059] The hardware structure of the IC card system in the present embodiment is identical with the IC card system in embodiment 1 (see figure 1 ). Moreover, when the processor 400 of this embodiment is used, the division of the memory space divided into a plurality of regions is also the same as in Embodiment 1 (see Figure 7 ).

[0060] image 3 is a conceptual diagram of programs used in processor 400 of this embodiment.

[0061] The API program 602 in the API storage space includes a branch enabling instruction (accept usr), which is used to determine the API area when the execution is transferred from the user program 603 in the user area to the API program 602 in the API area by a branch instruction (jmp). Whether the branch destination address in is valid.

[0062] The supervisor program 601 in the supervisor area also includes a branch en...

Embodiment 3

[0078] The following is a description of an IC card system using the processor 400 of Embodiment 3 of the present invention.

[0079] The hardware structure of the IC card system in the present embodiment is identical with the IC card system in embodiment 1 (see figure 1 ). Moreover, when the processor 400 of this embodiment is used, the division of the memory space divided into a plurality of regions is also the same as in Embodiment 1 (see Figure 7 ). .

[0080] image 3 is a conceptual diagram of programs used in processor 400 of this embodiment.

[0081] The API program 602 in the API area includes a branch enabling instruction (accept usr), which is used to determine the API program 602 in the API area when the execution is transferred from the user program 603 in the user area to the API program 602 in the API area by a branch instruction (jmp). Whether the branch destination address of the branch is valid.

[0082] The supervisor program 601 in the supervisor ar...

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PUM

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Abstract

The present invention provides a processor that can prevent a supervisor program from being executed incorrectly by a user program so as to ensure security and can improve the real time performance for a valid branch from the user program to the supervisor program. The processor 400 includes a CPU 401, a flash memory 404 for storing a program, and a invalid branch detection circuit 409. When branch instruction that changes an operation mode to another operation mode is executed by the program stored in the flash memory 404, the invalid branch detection circuit 409 determines whether there is a branch enable instruction in a branch destination address. In the absence of the branch enable instruction, the invalid branch detection circuit 409 outputs an invalid branch detection signal, thus preventing the supervisor program from being executed incorrectly by the user program.

Description

technical field [0001] This invention relates to processors, and more particularly to branch instructions for controlling the operation of a processor. Background technique [0002] The processor generally executes various types of processing such as data processing and arithmetic processing according to programs stored in an instruction memory. [0003] The above-mentioned conventional processor will be described with reference to the accompanying drawings. [0004] Image 6 is a block diagram showing an IC card system using a processor developed by conventional techniques. [0005] Such as Image 6 Shown, IC card system comprises following: CPU 101; Instruction ROM (read-only memory) 102; RAM (random access memory) 103; Flash memory 104; External I / F 105; Antenna coil 106; Address bus 107a; Data bus 107d; an interrupt control circuit 108; and a branch enable address judgment circuit 109. [0006] The CPU 101 includes an instruction retrieval unit 1011 , an instruction d...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/318G06F9/32G06F9/38G06F9/42
CPCG06F9/4426G06F9/30181G06F9/3861G06F9/30058G06F9/30076G06F9/30189G06F9/4486G06F9/323
Inventor 深井慎一郎甲斐俊也
Owner PANASONIC CORP
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